Simulation Results: clkmgr

 
23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.36 %
  • code
  • 98.20 %
  • assert
  • 95.76 %
  • func
  • 86.11 %
  • line
  • 98.95 %
  • branch
  • 98.48 %
  • cond
  • 94.36 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.770s 19.052us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.810s 65.787us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.800s 19.533us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 12.120s 4223.299us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 2.310s 596.183us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.020s 25.827us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.800s 19.533us 1 1 100.00
clkmgr_csr_aliasing 2.310s 596.183us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.830s 45.656us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.090s 230.260us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.850s 78.095us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.700s 47.259us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.770s 19.052us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 2.570s 923.819us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 1.360s 288.780us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 2.570s 923.819us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 14.450s 5942.298us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.850s 17.422us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.610s 39.646us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.610s 39.646us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.810s 65.787us 1 1 100.00
clkmgr_csr_rw 0.800s 19.533us 1 1 100.00
clkmgr_csr_aliasing 2.310s 596.183us 1 1 100.00
clkmgr_same_csr_outstanding 0.880s 29.991us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.810s 65.787us 1 1 100.00
clkmgr_csr_rw 0.800s 19.533us 1 1 100.00
clkmgr_csr_aliasing 2.310s 596.183us 1 1 100.00
clkmgr_same_csr_outstanding 0.880s 29.991us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 25.790s 10066.021us 0 1 0.00
clkmgr_tl_intg_err 41.170s 10089.053us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.120s 142.515us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.120s 142.515us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.120s 142.515us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.120s 142.515us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 3.140s 678.646us 1 1 100.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 41.170s 10089.053us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 2.570s 923.819us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 1.360s 288.780us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.120s 142.515us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.780s 32.462us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.830s 61.410us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.900s 23.471us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 1.030s 95.030us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.830s 68.465us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.800s 19.533us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 25.790s 10066.021us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.800s 19.533us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.800s 19.533us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 25.790s 10066.021us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 1.510s 318.383us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 126.950s 47438.718us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 2 test runs
clkmgr_sec_cm 34596599145622460956726224665182273701188078684663867529331597590722009776861 101
UVM_INFO @ 10066021448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 20974290227330376758344316099591561617810289777055259426669825033986370233683 182
UVM_INFO @ 10089053295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---