Simulation Results: csrng

 
23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.91 %
  • code
  • 92.36 %
  • assert
  • 94.54 %
  • func
  • 79.84 %
  • block
  • 97.05 %
  • line
  • 97.73 %
  • branch
  • 92.68 %
  • toggle
  • 93.31 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 54.937us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 3.000s 305.021us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 1.000s 30.094us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 12.000s 491.020us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 6.000s 325.489us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 160.162us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 1.000s 30.094us 1 1 100.00
csrng_csr_aliasing 6.000s 325.489us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 13.000s 1319.352us 1 1 100.00
alerts 1 1 100.00
csrng_alert 15.000s 1115.873us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 22.090us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 4.000s 117.662us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 4.000s 117.662us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 428.000s 16654.165us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 16.903us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 3.000s 47.174us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 6.000s 123.154us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 6.000s 123.154us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 3.000s 305.021us 1 1 100.00
csrng_csr_rw 1.000s 30.094us 1 1 100.00
csrng_csr_aliasing 6.000s 325.489us 1 1 100.00
csrng_same_csr_outstanding 3.000s 32.111us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 3.000s 305.021us 1 1 100.00
csrng_csr_rw 1.000s 30.094us 1 1 100.00
csrng_csr_aliasing 6.000s 325.489us 1 1 100.00
csrng_same_csr_outstanding 3.000s 32.111us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 2.000s 71.966us 1 1 100.00
csrng_tl_intg_err 10.000s 1223.503us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 2.000s 12.062us 0 1 0.00
csrng_csr_rw 1.000s 30.094us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 15.000s 1115.873us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 428.000s 16654.165us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 13.000s 1319.352us 1 1 100.00
csrng_err 2.000s 22.090us 1 1 100.00
csrng_sec_cm 2.000s 71.966us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 13.000s 1319.352us 1 1 100.00
csrng_err 2.000s 22.090us 1 1 100.00
csrng_sec_cm 2.000s 71.966us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 13.000s 1319.352us 1 1 100.00
csrng_err 2.000s 22.090us 1 1 100.00
csrng_sec_cm 2.000s 71.966us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 13.000s 1319.352us 1 1 100.00
csrng_err 2.000s 22.090us 1 1 100.00
csrng_sec_cm 2.000s 71.966us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 13.000s 1319.352us 1 1 100.00
csrng_err 2.000s 22.090us 1 1 100.00
csrng_sec_cm 2.000s 71.966us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 15.000s 1115.873us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 13.000s 1319.352us 1 1 100.00
csrng_err 2.000s 22.090us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 428.000s 16654.165us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 15.000s 1115.873us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 10.000s 1223.503us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 13.000s 1319.352us 1 1 100.00
csrng_err 2.000s 22.090us 1 1 100.00
csrng_sec_cm 2.000s 71.966us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 13.000s 1319.352us 1 1 100.00
csrng_err 2.000s 22.090us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 13.000s 1319.352us 1 1 100.00
csrng_err 2.000s 22.090us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 13.000s 1319.352us 1 1 100.00
csrng_err 2.000s 22.090us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 13.000s 1319.352us 1 1 100.00
csrng_err 2.000s 22.090us 1 1 100.00
csrng_sec_cm 2.000s 71.966us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 13.000s 1319.352us 1 1 100.00
csrng_err 2.000s 22.090us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 1.000s 1.108us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE 1 test run
csrng_regwen 15737620229620098887978150969217899976486668490590859752044241090059759464151 99
UVM_INFO @ 12062054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started 1 test run
csrng_stress_all_with_rand_reset 109533198212341907372604228092387503610153031561520126720071378336021246530965 104
UVM_INFO @ 1108011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---