Simulation Results: edn/edn0

 
23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.12 %
  • code
  • 73.70 %
  • assert
  • 93.49 %
  • func
  • 79.17 %
  • line
  • 95.60 %
  • branch
  • 84.94 %
  • cond
  • 80.50 %
  • toggle
  • 66.60 %
  • FSM
  • 40.86 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.890s 18.841us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.740s 39.537us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.850s 83.246us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.270s 1731.807us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.190s 141.762us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.020s 63.642us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.850s 83.246us 1 1 100.00
edn_csr_aliasing 1.190s 141.762us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.420s 59.757us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.420s 59.757us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.420s 59.757us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.110s 23.384us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.060s 43.455us 1 1 100.00
errs 1 1 100.00
edn_err 1.070s 27.530us 1 1 100.00
disable 1 2 50.00
edn_disable 0.910s 22.599us 1 1 100.00
edn_disable_auto_req_mode 1.550s 500.000us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 2.310s 141.366us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.840s 24.894us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.850s 54.291us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.130s 64.770us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.130s 64.770us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.740s 39.537us 1 1 100.00
edn_csr_rw 0.850s 83.246us 1 1 100.00
edn_csr_aliasing 1.190s 141.762us 1 1 100.00
edn_same_csr_outstanding 1.020s 91.685us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.740s 39.537us 1 1 100.00
edn_csr_rw 0.850s 83.246us 1 1 100.00
edn_csr_aliasing 1.190s 141.762us 1 1 100.00
edn_same_csr_outstanding 1.020s 91.685us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 10.520s 984.295us 1 1 100.00
edn_tl_intg_err 1.590s 82.296us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.920s 24.637us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.060s 43.455us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 10.520s 984.295us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 10.520s 984.295us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 10.520s 984.295us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 10.520s 984.295us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.060s 43.455us 1 1 100.00
edn_sec_cm 10.520s 984.295us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.060s 43.455us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.590s 82.296us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 32.060s 3989.346us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
edn_disable_auto_req_mode 6158409614973140151110315248939776280540513915925614357881654978761564766243 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---