Simulation Results: edn/edn1

 
23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.56 %
  • code
  • 84.63 %
  • assert
  • 98.44 %
  • func
  • 79.62 %
  • line
  • 98.18 %
  • branch
  • 93.29 %
  • cond
  • 88.77 %
  • toggle
  • 95.19 %
  • FSM
  • 47.73 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.010s 41.530us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.750s 53.040us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.790s 23.134us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.820s 226.495us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.930s 15.765us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.980s 97.563us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.790s 23.134us 1 1 100.00
edn_csr_aliasing 0.930s 15.765us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.030s 30.922us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.030s 30.922us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.030s 30.922us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 23.674us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.000s 108.602us 1 1 100.00
errs 1 1 100.00
edn_err 1.140s 18.630us 1 1 100.00
disable 2 2 100.00
edn_disable 0.770s 13.570us 1 1 100.00
edn_disable_auto_req_mode 1.060s 32.529us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.910s 524.797us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.730s 67.378us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.910s 20.515us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.570s 240.300us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.570s 240.300us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.750s 53.040us 1 1 100.00
edn_csr_rw 0.790s 23.134us 1 1 100.00
edn_csr_aliasing 0.930s 15.765us 1 1 100.00
edn_same_csr_outstanding 1.110s 32.056us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.750s 53.040us 1 1 100.00
edn_csr_rw 0.790s 23.134us 1 1 100.00
edn_csr_aliasing 0.930s 15.765us 1 1 100.00
edn_same_csr_outstanding 1.110s 32.056us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.340s 688.609us 1 1 100.00
edn_tl_intg_err 1.340s 153.433us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.740s 25.679us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.000s 108.602us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.340s 688.609us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.340s 688.609us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.340s 688.609us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.340s 688.609us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.000s 108.602us 1 1 100.00
edn_sec_cm 2.340s 688.609us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.000s 108.602us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.340s 153.433us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 47.790s 11663.193us 1 1 100.00