Simulation Results: entropy_src/rng_4bits

 
23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.80 %
  • code
  • 88.25 %
  • assert
  • 84.24 %
  • func
  • 51.92 %
  • block
  • 94.41 %
  • line
  • 97.11 %
  • branch
  • 86.53 %
  • toggle
  • 75.60 %
  • FSM
  • 93.75 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 34.578us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 1.000s 42.318us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 1.000s 26.180us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 6.000s 873.417us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 4.000s 743.041us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 9.769us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 1.000s 26.180us 1 1 100.00
entropy_src_csr_aliasing 4.000s 743.041us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 34.578us 1 1 100.00
entropy_src_rng 56.000s 13118.403us 1 1 100.00
entropy_src_fw_ov 15.000s 13238.164us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 15.000s 13238.164us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 56.000s 13118.403us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 190.000s 14070.459us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 56.000s 13118.403us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 56.000s 13118.403us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 56.000s 13118.403us 1 1 100.00
entropy_src_intr 3.000s 272.429us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 56.000s 13118.403us 1 1 100.00
entropy_src_functional_alerts 4.000s 837.745us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 163.000s 14185.544us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 195.517us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 3.000s 58.683us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 56.711us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 1.000s 161.224us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 2.000s 52.940us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 2.000s 52.940us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 1.000s 42.318us 1 1 100.00
entropy_src_csr_rw 1.000s 26.180us 1 1 100.00
entropy_src_csr_aliasing 4.000s 743.041us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 53.665us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 1.000s 42.318us 1 1 100.00
entropy_src_csr_rw 1.000s 26.180us 1 1 100.00
entropy_src_csr_aliasing 4.000s 743.041us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 53.665us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 57.833us 1 1 100.00
entropy_src_tl_intg_err 4.000s 119.095us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 56.000s 13118.403us 1 1 100.00
entropy_src_cfg_regwen 1.000s 16.533us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 56.000s 13118.403us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 56.000s 13118.403us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 56.000s 13118.403us 1 1 100.00
entropy_src_fw_ov 15.000s 13238.164us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 195.517us 1 1 100.00
entropy_src_sec_cm 2.000s 57.833us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 195.517us 1 1 100.00
entropy_src_sec_cm 2.000s 57.833us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 56.000s 13118.403us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 195.517us 1 1 100.00
entropy_src_sec_cm 2.000s 57.833us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 195.517us 1 1 100.00
entropy_src_sec_cm 2.000s 57.833us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 195.517us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 4.000s 837.745us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 4.000s 119.095us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 198.000s 13092.901us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 1.000s 31.681us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror repcnts_total_fails 1 test run
entropy_src_stress_all_with_rand_reset 33458207374599181834828385220250801175262569301051633865575220293780523884348 112
UVM_INFO @ 31681241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_hi_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 64048229050974246839225369580134137250836183312058962495141277228649395658352 113
UVM_INFO @ 9768946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---