Simulation Results: flash_ctrl

 
23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.17 %
  • code
  • 93.83 %
  • assert
  • 96.94 %
  • func
  • 94.74 %
  • line
  • 95.97 %
  • branch
  • 97.08 %
  • cond
  • 93.84 %
  • toggle
  • 97.91 %
  • FSM
  • 84.35 %
Validation stages
V1
100.00%
V2
100.00%
V2S
95.83%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 43.630s 101.983us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 12.800s 33.085us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 15.880s 34.238us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 10.070s 251.988us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 32.200s 3655.578us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 22.310s 2902.331us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.990s 157.362us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 10.070s 251.988us 1 1 100.00
flash_ctrl_csr_aliasing 22.310s 2902.331us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 7.040s 17.946us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 8.850s 19.525us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 14.190s 25.603us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 24.580s 172.516us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1253.020s 184863.034us 1 1 100.00
flash_ctrl_hw_rma_reset 529.480s 40127.900us 1 1 100.00
flash_ctrl_lcmgr_intg 8.320s 23.582us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1054.250s 558734.395us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 128.390s 1563.336us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 122.770s 10803.206us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2000.330s 461956.067us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 60.960s 1427.204us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 18.810s 56.322us 1 1 100.00
flash_ctrl_rw_evict_all_en 17.310s 173.471us 1 1 100.00
flash_ctrl_re_evict 18.510s 84.630us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 85.790s 60.961us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 85.790s 60.961us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 106.840s 30547.406us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 13.830s 414.633us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 183.400s 205.118us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 363.390s 12593.325us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 349.930s 5895.297us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 813.490s 1742.083us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 6.200s 83.453us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 109.010s 8742.065us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 11.270s 35.086us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.710s 25.198us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 254.200s 203.421us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 78.090s 4108.034us 1 1 100.00
flash_ctrl_otp_reset 52.850s 73.313us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1253.020s 184863.034us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 159.490s 4098.477us 1 1 100.00
flash_ctrl_intr_wr 55.870s 6972.923us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 91.390s 6127.507us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 150.960s 73347.205us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 44.100s 2334.205us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 40.650s 3932.759us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 11.540s 33.077us 1 1 100.00
flash_ctrl_ro_derr 117.650s 1063.742us 1 1 100.00
flash_ctrl_rw_derr 141.480s 10409.851us 1 1 100.00
flash_ctrl_derr_detect 88.350s 551.859us 1 1 100.00
flash_ctrl_integrity 415.530s 3963.188us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 10.620s 30.483us 1 1 100.00
flash_ctrl_ro_serr 99.610s 1076.463us 1 1 100.00
flash_ctrl_rw_serr 132.210s 1890.466us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 40.300s 2732.836us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 47.340s 3304.340us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 83.290s 2363.296us 1 1 100.00
flash_ctrl_write_word_sweep 6.970s 164.817us 1 1 100.00
flash_ctrl_read_word_sweep 7.750s 512.214us 1 1 100.00
flash_ctrl_ro 81.230s 1367.691us 1 1 100.00
flash_ctrl_rw 369.140s 16266.041us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 18.750s 2229.363us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 544.420s 108666.676us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 77.270s 10020.593us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 7.420s 79.602us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 5.880s 64.695us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 13.240s 138.016us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 13.240s 138.016us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 15.880s 34.238us 1 1 100.00
flash_ctrl_csr_rw 10.070s 251.988us 1 1 100.00
flash_ctrl_csr_aliasing 22.310s 2902.331us 1 1 100.00
flash_ctrl_same_csr_outstanding 11.140s 71.092us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 15.880s 34.238us 1 1 100.00
flash_ctrl_csr_rw 10.070s 251.988us 1 1 100.00
flash_ctrl_csr_aliasing 22.310s 2902.331us 1 1 100.00
flash_ctrl_same_csr_outstanding 11.140s 71.092us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 35.200s 149.745us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 35.200s 149.745us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 35.200s 149.745us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 35.200s 149.745us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 19.080s 136.194us 1 1 100.00
tl_intg_err 1 2 50.00
flash_ctrl_sec_cm 1769.700s 1852.179us 1 1 100.00
flash_ctrl_tl_intg_err 78.350s 10160.302us 0 1 0.00
sec_cm_reg_bus_integrity 0 1 0.00
flash_ctrl_tl_intg_err 78.350s 10160.302us 0 1 0.00
sec_cm_host_bus_integrity 0 1 0.00
flash_ctrl_tl_intg_err 78.350s 10160.302us 0 1 0.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 16.290s 111.444us 1 1 100.00
flash_ctrl_wr_intg 7.130s 179.168us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 43.630s 101.983us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 52.850s 73.313us 1 1 100.00
flash_ctrl_disable 11.270s 35.086us 1 1 100.00
flash_ctrl_sec_info_access 50.530s 17260.260us 1 1 100.00
flash_ctrl_connect 7.710s 25.198us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.470s 155.310us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 10.070s 251.988us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 35.200s 149.745us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 10.070s 251.988us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 35.200s 149.745us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 10.070s 251.988us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 35.200s 149.745us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 11.270s 35.086us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 16.290s 111.444us 1 1 100.00
flash_ctrl_access_after_disable 6.060s 38.654us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 12.760s 67.020us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 11.270s 35.086us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 13.830s 414.633us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 369.140s 16266.041us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 132.210s 1890.466us 1 1 100.00
flash_ctrl_rw_derr 141.480s 10409.851us 1 1 100.00
flash_ctrl_integrity 415.530s 3963.188us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1253.020s 184863.034us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1769.700s 1852.179us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1769.700s 1852.179us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1769.700s 1852.179us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1769.700s 1852.179us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 10.570s 932.760us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 8.090s 23.144us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.940s 63.727us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1769.700s 1852.179us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1769.700s 1852.179us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1769.700s 1852.179us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 24.160s 142.531us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 40.840s 98.850us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:465) [flash_ctrl_common_vseq] wait timeout occurred! 1 test run
flash_ctrl_tl_intg_err 81726195495827551680457194617258243530946069483046282635905627802311614280436 183
UVM_INFO @ 10160302.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---