Simulation Results: hmac

 
23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.87 %
  • code
  • 97.95 %
  • assert
  • 97.60 %
  • func
  • 44.07 %
  • line
  • 99.69 %
  • branch
  • 99.50 %
  • cond
  • 96.46 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 3.710s 138.124us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.740s 64.205us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.790s 17.599us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.830s 2628.713us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.700s 390.307us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.220s 29.004us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.790s 17.599us 1 1 100.00
hmac_csr_aliasing 4.700s 390.307us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 33.310s 19749.114us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 13.600s 393.971us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 222.020s 42430.101us 1 1 100.00
hmac_test_sha384_vectors 21.170s 676.491us 1 1 100.00
hmac_test_sha512_vectors 340.000s 14348.368us 1 1 100.00
hmac_test_hmac256_vectors 8.600s 366.013us 1 1 100.00
hmac_test_hmac384_vectors 9.420s 1649.719us 1 1 100.00
hmac_test_hmac512_vectors 9.280s 371.621us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 17.000s 2338.695us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 148.760s 7149.058us 1 1 100.00
error 1 1 100.00
hmac_error 40.230s 1485.252us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 39.910s 1610.466us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 3.710s 138.124us 1 1 100.00
hmac_long_msg 33.310s 19749.114us 1 1 100.00
hmac_back_pressure 13.600s 393.971us 1 1 100.00
hmac_datapath_stress 148.760s 7149.058us 1 1 100.00
hmac_burst_wr 17.000s 2338.695us 1 1 100.00
hmac_stress_all 326.140s 11320.263us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 3.710s 138.124us 1 1 100.00
hmac_long_msg 33.310s 19749.114us 1 1 100.00
hmac_back_pressure 13.600s 393.971us 1 1 100.00
hmac_datapath_stress 148.760s 7149.058us 1 1 100.00
hmac_wipe_secret 39.910s 1610.466us 1 1 100.00
hmac_test_sha256_vectors 222.020s 42430.101us 1 1 100.00
hmac_test_sha384_vectors 21.170s 676.491us 1 1 100.00
hmac_test_sha512_vectors 340.000s 14348.368us 1 1 100.00
hmac_test_hmac256_vectors 8.600s 366.013us 1 1 100.00
hmac_test_hmac384_vectors 9.420s 1649.719us 1 1 100.00
hmac_test_hmac512_vectors 9.280s 371.621us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 3.710s 138.124us 1 1 100.00
hmac_long_msg 33.310s 19749.114us 1 1 100.00
hmac_back_pressure 13.600s 393.971us 1 1 100.00
hmac_datapath_stress 148.760s 7149.058us 1 1 100.00
hmac_burst_wr 17.000s 2338.695us 1 1 100.00
hmac_error 40.230s 1485.252us 1 1 100.00
hmac_wipe_secret 39.910s 1610.466us 1 1 100.00
hmac_test_sha256_vectors 222.020s 42430.101us 1 1 100.00
hmac_test_sha384_vectors 21.170s 676.491us 1 1 100.00
hmac_test_sha512_vectors 340.000s 14348.368us 1 1 100.00
hmac_test_hmac256_vectors 8.600s 366.013us 1 1 100.00
hmac_test_hmac384_vectors 9.420s 1649.719us 1 1 100.00
hmac_test_hmac512_vectors 9.280s 371.621us 1 1 100.00
hmac_stress_all 326.140s 11320.263us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 326.140s 11320.263us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.680s 10.825us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.680s 23.602us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.840s 379.336us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.840s 379.336us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.740s 64.205us 1 1 100.00
hmac_csr_rw 0.790s 17.599us 1 1 100.00
hmac_csr_aliasing 4.700s 390.307us 1 1 100.00
hmac_same_csr_outstanding 1.840s 180.284us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.740s 64.205us 1 1 100.00
hmac_csr_rw 0.790s 17.599us 1 1 100.00
hmac_csr_aliasing 4.700s 390.307us 1 1 100.00
hmac_same_csr_outstanding 1.840s 180.284us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.770s 177.967us 1 1 100.00
hmac_tl_intg_err 2.500s 94.721us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.500s 94.721us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 3.710s 138.124us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.190s 477.193us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 89.530s 3167.096us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.910s 20.808us 1 1 100.00