Simulation Results: i2c

 
23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.18 %
  • code
  • 81.49 %
  • assert
  • 97.46 %
  • func
  • 79.60 %
  • line
  • 96.45 %
  • branch
  • 92.41 %
  • cond
  • 85.34 %
  • toggle
  • 88.61 %
  • FSM
  • 44.64 %
Validation stages
V1
100.00%
V2
90.24%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 36.840s 5723.352us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 14.740s 779.496us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.930s 123.415us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.700s 56.029us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 2.510s 1121.118us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.190s 136.241us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.790s 91.714us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.700s 56.029us 1 1 100.00
i2c_csr_aliasing 1.190s 136.241us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 1 1 100.00
i2c_host_error_intr 1.040s 82.686us 1 1 100.00
host_stress_all 0 1 0.00
i2c_host_stress_all 399.380s 38016.736us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 81.130s 25760.600us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.650s 48.580us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 31.090s 2752.535us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 48.920s 7552.811us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.880s 528.128us 1 1 100.00
i2c_host_fifo_fmt_empty 3.120s 2675.886us 1 1 100.00
i2c_host_fifo_reset_rx 2.150s 118.020us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 105.470s 3107.007us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 21.050s 1034.404us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 2.880s 546.145us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 1.690s 600.903us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 24.640s 7620.127us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 4.530s 1682.698us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 7.040s 896.139us 1 1 100.00
i2c_target_intr_smoke 4.160s 1724.430us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.170s 243.389us 1 1 100.00
i2c_target_fifo_reset_tx 1.390s 431.305us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 79.380s 36482.284us 1 1 100.00
i2c_target_stress_rd 7.040s 896.139us 1 1 100.00
i2c_target_intr_stress_wr 27.540s 19951.529us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 3.910s 993.298us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 18.400s 4374.301us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 3.820s 4141.243us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 2.040s 601.627us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.990s 746.658us 1 1 100.00
i2c_target_fifo_watermarks_tx 0.900s 127.076us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 81.130s 25760.600us 1 1 100.00
i2c_host_perf_precise 33.670s 24710.866us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 21.050s 1034.404us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 2.590s 148.445us 1 1 100.00
target_mode_nack_generation 2 3 66.67
i2c_target_nack_acqfull 1.840s 898.565us 1 1 100.00
i2c_target_nack_acqfull_addr 1.690s 5269.346us 1 1 100.00
i2c_target_nack_txstretch 1.020s 476.041us 0 1 0.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 7.820s 1982.486us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.640s 984.389us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.830s 43.940us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.840s 15.860us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.900s 433.552us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.900s 433.552us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.930s 123.415us 1 1 100.00
i2c_csr_rw 0.700s 56.029us 1 1 100.00
i2c_csr_aliasing 1.190s 136.241us 1 1 100.00
i2c_same_csr_outstanding 1.150s 292.627us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.930s 123.415us 1 1 100.00
i2c_csr_rw 0.700s 56.029us 1 1 100.00
i2c_csr_aliasing 1.190s 136.241us 1 1 100.00
i2c_same_csr_outstanding 1.150s 292.627us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 2.120s 569.692us 1 1 100.00
i2c_sec_cm 0.830s 56.616us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 2.120s 569.692us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 23.560s 785.851us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.460s 508.267us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 13.480s 2575.916us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: 2 test runs
i2c_host_stress_all 28198642382417986104538335455726171701573709041204548170451633784261788483 142
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3476132
i2c_host_mode_toggle 7308923806303486411095851794947668799085836871001322358876815304407525582921 85
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @70181
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
i2c_host_stress_all_with_rand_reset 59442973693985037819050312937343078018246999286466389914011613477264521492969 89
UVM_INFO @ 785851472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 58024759376333599196689571213872306165810173335339394653702304440370898472737 97
UVM_INFO @ 2575916047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 82546805158139220180162819710126179992414027838458574788710530554707560523336 84
UVM_INFO @ 600902578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 112223531472347354346747410646713444041255689738363392421498851068823831712815 78
UVM_INFO @ 508267450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * 1 test run
i2c_target_nack_txstretch 112086380588326513743846883101777404638043465385997518469402993855415042304118 78
UVM_INFO @ 476040997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---