Simulation Results: keymgr

 
23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.31 %
  • code
  • 94.84 %
  • assert
  • 97.49 %
  • func
  • 57.61 %
  • line
  • 98.76 %
  • branch
  • 97.63 %
  • cond
  • 93.72 %
  • toggle
  • 95.70 %
  • FSM
  • 88.37 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 2.420s 328.432us 1 1 100.00
random 1 1 100.00
keymgr_random 1.850s 92.288us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.670s 35.060us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.360s 109.469us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 4.960s 203.289us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 4.110s 905.256us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.530s 163.357us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.360s 109.469us 1 1 100.00
keymgr_csr_aliasing 4.110s 905.256us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 7.590s 485.560us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 2.050s 90.877us 1 1 100.00
keymgr_sideload_kmac 2.960s 139.494us 1 1 100.00
keymgr_sideload_aes 3.710s 254.695us 1 1 100.00
keymgr_sideload_otbn 2.230s 60.650us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 1.710s 30.842us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 2.130s 181.520us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 3.300s 1013.735us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 6.630s 311.960us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 1.570s 113.329us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.450s 30.090us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 13.370s 8146.095us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.970s 41.301us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.840s 11.991us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 1.790s 48.730us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 1.790s 48.730us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.670s 35.060us 1 1 100.00
keymgr_csr_rw 1.360s 109.469us 1 1 100.00
keymgr_csr_aliasing 4.110s 905.256us 1 1 100.00
keymgr_same_csr_outstanding 3.170s 114.782us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.670s 35.060us 1 1 100.00
keymgr_csr_rw 1.360s 109.469us 1 1 100.00
keymgr_csr_aliasing 4.110s 905.256us 1 1 100.00
keymgr_same_csr_outstanding 3.170s 114.782us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 10.770s 735.415us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 10.770s 735.415us 1 1 100.00
keymgr_tl_intg_err 6.790s 1362.486us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 2.340s 131.372us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 2.340s 131.372us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 2.340s 131.372us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 2.340s 131.372us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 8.090s 516.567us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 10.770s 735.415us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 10.770s 735.415us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 6.790s 1362.486us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 2.340s 131.372us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 7.590s 485.560us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 1.850s 92.288us 1 1 100.00
keymgr_csr_rw 1.360s 109.469us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 1.850s 92.288us 1 1 100.00
keymgr_csr_rw 1.360s 109.469us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 1.850s 92.288us 1 1 100.00
keymgr_csr_rw 1.360s 109.469us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 2.130s 181.520us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.570s 113.329us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.570s 113.329us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 1.850s 92.288us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 2.700s 367.668us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 10.770s 735.415us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 10.770s 735.415us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 10.770s 735.415us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 2.500s 146.337us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 2.130s 181.520us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 10.770s 735.415us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 10.770s 735.415us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 10.770s 735.415us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.500s 146.337us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.500s 146.337us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 10.770s 735.415us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.500s 146.337us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 10.770s 735.415us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 2.500s 146.337us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 6.910s 1561.722us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
keymgr_stress_all_with_rand_reset 68637010548931249256486937471128311947538007621936700493400772632484162397497 995
UVM_INFO @ 1561721672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---