| V1 |
|
100.00% |
| V2 |
|
68.97% |
| V2S |
|
87.50% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| kmac_smoke | 35.210s | 5077.596us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| kmac_csr_hw_reset | 0.790s | 54.028us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| kmac_csr_rw | 0.930s | 21.545us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| kmac_csr_bit_bash | 14.830s | 2768.771us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| kmac_csr_aliasing | 4.830s | 145.407us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| kmac_csr_mem_rw_with_rand_reset | 1.420s | 49.949us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| kmac_csr_rw | 0.930s | 21.545us | 1 | 1 | 100.00 | |
| kmac_csr_aliasing | 4.830s | 145.407us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| kmac_mem_walk | 0.760s | 76.260us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| kmac_mem_partial_access | 1.450s | 38.125us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| long_msg_and_output | 1 | 1 | 100.00 | |||
| kmac_long_msg_and_output | 2132.780s | 141219.650us | 1 | 1 | 100.00 | |
| burst_write | 1 | 1 | 100.00 | |||
| kmac_burst_write | 615.890s | 129782.279us | 1 | 1 | 100.00 | |
| test_vectors | 8 | 8 | 100.00 | |||
| kmac_test_vectors_sha3_224 | 1362.500s | 100319.146us | 1 | 1 | 100.00 | |
| kmac_test_vectors_sha3_256 | 2046.150s | 92634.716us | 1 | 1 | 100.00 | |
| kmac_test_vectors_sha3_384 | 1194.460s | 71459.938us | 1 | 1 | 100.00 | |
| kmac_test_vectors_sha3_512 | 11.220s | 371.870us | 1 | 1 | 100.00 | |
| kmac_test_vectors_shake_128 | 106.110s | 6314.037us | 1 | 1 | 100.00 | |
| kmac_test_vectors_shake_256 | 299.460s | 27925.894us | 1 | 1 | 100.00 | |
| kmac_test_vectors_kmac | 1.880s | 160.479us | 1 | 1 | 100.00 | |
| kmac_test_vectors_kmac_xof | 1.880s | 61.067us | 1 | 1 | 100.00 | |
| sideload | 1 | 1 | 100.00 | |||
| kmac_sideload | 160.080s | 11703.093us | 1 | 1 | 100.00 | |
| app | 0 | 1 | 0.00 | |||
| kmac_app | 2.130s | 309.969us | 0 | 1 | 0.00 | |
| app_with_partial_data | 0 | 1 | 0.00 | |||
| kmac_app_with_partial_data | 5.230s | 324.650us | 0 | 1 | 0.00 | |
| entropy_refresh | 0 | 1 | 0.00 | |||
| kmac_entropy_refresh | 5.140s | 1350.486us | 0 | 1 | 0.00 | |
| error | 0 | 1 | 0.00 | |||
| kmac_error | 46.380s | 2054.562us | 0 | 1 | 0.00 | |
| key_error | 0 | 1 | 0.00 | |||
| kmac_key_error | 1.090s | 128.366us | 0 | 1 | 0.00 | |
| sideload_invalid | 0 | 1 | 0.00 | |||
| kmac_sideload_invalid | 0.840s | 11.694us | 0 | 1 | 0.00 | |
| edn_timeout_error | 0 | 1 | 0.00 | |||
| kmac_edn_timeout_error | 6.690s | 1102.574us | 0 | 1 | 0.00 | |
| entropy_mode_error | 1 | 1 | 100.00 | |||
| kmac_entropy_mode_error | 3.770s | 84.864us | 1 | 1 | 100.00 | |
| entropy_ready_error | 0 | 1 | 0.00 | |||
| kmac_entropy_ready_error | 0.850s | 50.951us | 0 | 1 | 0.00 | |
| lc_escalation | 1 | 1 | 100.00 | |||
| kmac_lc_escalation | 1.290s | 128.168us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| kmac_stress_all | 2.700s | 228.617us | 0 | 1 | 0.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| kmac_intr_test | 0.890s | 26.475us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| kmac_alert_test | 0.840s | 25.011us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| kmac_tl_errors | 2.300s | 1818.626us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| kmac_tl_errors | 2.300s | 1818.626us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| kmac_csr_hw_reset | 0.790s | 54.028us | 1 | 1 | 100.00 | |
| kmac_csr_rw | 0.930s | 21.545us | 1 | 1 | 100.00 | |
| kmac_csr_aliasing | 4.830s | 145.407us | 1 | 1 | 100.00 | |
| kmac_same_csr_outstanding | 2.130s | 182.370us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| kmac_csr_hw_reset | 0.790s | 54.028us | 1 | 1 | 100.00 | |
| kmac_csr_rw | 0.930s | 21.545us | 1 | 1 | 100.00 | |
| kmac_csr_aliasing | 4.830s | 145.407us | 1 | 1 | 100.00 | |
| kmac_same_csr_outstanding | 2.130s | 182.370us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 1.010s | 84.685us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 1.010s | 84.685us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 1.010s | 84.685us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 1.010s | 84.685us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors_with_csr_rw | 2.570s | 445.999us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| kmac_sec_cm | 71.470s | 51292.455us | 1 | 1 | 100.00 | |
| kmac_tl_intg_err | 4.010s | 911.929us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| kmac_tl_intg_err | 4.010s | 911.929us | 1 | 1 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 1 | 1 | 100.00 | |||
| kmac_lc_escalation | 1.290s | 128.168us | 1 | 1 | 100.00 | |
| sec_cm_sw_key_key_masking | 1 | 1 | 100.00 | |||
| kmac_smoke | 35.210s | 5077.596us | 1 | 1 | 100.00 | |
| sec_cm_key_sideload | 1 | 1 | 100.00 | |||
| kmac_sideload | 160.080s | 11703.093us | 1 | 1 | 100.00 | |
| sec_cm_cfg_shadowed_config_shadow | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 1.010s | 84.685us | 1 | 1 | 100.00 | |
| sec_cm_fsm_sparse | 1 | 1 | 100.00 | |||
| kmac_sec_cm | 71.470s | 51292.455us | 1 | 1 | 100.00 | |
| sec_cm_ctr_redun | 1 | 1 | 100.00 | |||
| kmac_sec_cm | 71.470s | 51292.455us | 1 | 1 | 100.00 | |
| sec_cm_packer_ctr_redun | 1 | 1 | 100.00 | |||
| kmac_sec_cm | 71.470s | 51292.455us | 1 | 1 | 100.00 | |
| sec_cm_cfg_shadowed_config_regwen | 1 | 1 | 100.00 | |||
| kmac_smoke | 35.210s | 5077.596us | 1 | 1 | 100.00 | |
| sec_cm_fsm_global_esc | 1 | 1 | 100.00 | |||
| kmac_lc_escalation | 1.290s | 128.168us | 1 | 1 | 100.00 | |
| sec_cm_fsm_local_esc | 1 | 1 | 100.00 | |||
| kmac_sec_cm | 71.470s | 51292.455us | 1 | 1 | 100.00 | |
| sec_cm_absorbed_ctrl_mubi | 0 | 1 | 0.00 | |||
| kmac_mubi | 1.040s | 34.324us | 0 | 1 | 0.00 | |
| sec_cm_sw_cmd_ctrl_sparse | 1 | 1 | 100.00 | |||
| kmac_smoke | 35.210s | 5077.596us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| kmac_stress_all_with_rand_reset | 41.310s | 9666.930us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] | 8 test runs | |||
| kmac_sideload_invalid | 58763971379914570571971401265551053314831478455273655839661489168607944190875 | 76 |
UVM_INFO @ 11694089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_app | 113838367413601042754351702902467614685801030796102246054428066454528486968539 | 78 |
UVM_INFO @ 309968903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_app_with_partial_data | 78288447460992020259793945080477467706013626055699968531490560766977186362632 | 79 |
UVM_INFO @ 324649909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_entropy_refresh | 10614683871115895111010231858607869795600943570328979388783803764200745362972 | 79 |
UVM_INFO @ 1350486233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_error | 2245370739300642021124847816988269630407013655692431237808886963158169757177 | 111 |
UVM_INFO @ 2054562315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_entropy_ready_error | 87305210137441287491137889811243448445043059233805891089688752638103785716820 | 77 |
UVM_INFO @ 50950806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_stress_all | 14726673837565930869700725743801696073722394445505848258580229054923001340903 | 81 |
UVM_INFO @ 228617035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_stress_all_with_rand_reset | 104729790970911732397029094947059689381017154686040110948904372118045101520638 | 279 |
UVM_INFO @ 9666930419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))' | 2 test runs | |||
| kmac_key_error | 53419875001095271723999285412202815827010586865361252067617984692071017274477 | 78 |
UVM_ERROR @ 128365915 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 128365915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_edn_timeout_error | 77927380718914713746371924364177498375882822851342236041200046375326717518022 | 83 |
UVM_ERROR @ 1102573554 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 1102573554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err) | 1 test run | |||
| kmac_mubi | 22567848626564140112873835397715528960800935930600883773411365654142093954804 | 77 |
UVM_INFO @ 34324433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|