Simulation Results: lc_ctrl/volatile_unlock_enabled

 
23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.94 %
  • code
  • 83.81 %
  • assert
  • 94.69 %
  • func
  • 94.31 %
  • line
  • 97.04 %
  • branch
  • 93.08 %
  • cond
  • 78.58 %
  • toggle
  • 86.81 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.570s 31.215us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.130s 18.066us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.880s 180.724us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.260s 64.863us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.340s 38.131us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.370s 100.438us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.880s 180.724us 1 1 100.00
lc_ctrl_csr_aliasing 1.340s 38.131us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.880s 186.855us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.190s 551.638us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.780s 38.941us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.350s 89.025us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.930s 247.594us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 13.350s 627.835us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.930s 247.594us 1 1 100.00
lc_ctrl_prog_failure 1.350s 89.025us 1 1 100.00
lc_ctrl_errors 13.350s 627.835us 1 1 100.00
lc_ctrl_security_escalation 9.410s 467.012us 1 1 100.00
lc_ctrl_jtag_state_failure 45.510s 22350.015us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.060s 1121.919us 1 1 100.00
lc_ctrl_jtag_errors 32.330s 7953.408us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.500s 3157.145us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.080s 365.069us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.060s 1121.919us 1 1 100.00
lc_ctrl_jtag_errors 32.330s 7953.408us 1 1 100.00
lc_ctrl_jtag_access 4.040s 186.675us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.070s 982.064us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.500s 577.133us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.020s 49.321us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.940s 1869.859us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.600s 364.169us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.050s 23.084us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.660s 103.045us 1 1 100.00
lc_ctrl_jtag_alert_test 0.980s 146.316us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.340s 806.242us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.190s 54.142us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 62.710s 24517.453us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.170s 93.120us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.710s 77.380us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.710s 77.380us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.130s 18.066us 1 1 100.00
lc_ctrl_csr_rw 0.880s 180.724us 1 1 100.00
lc_ctrl_csr_aliasing 1.340s 38.131us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.380s 33.499us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.130s 18.066us 1 1 100.00
lc_ctrl_csr_rw 0.880s 180.724us 1 1 100.00
lc_ctrl_csr_aliasing 1.340s 38.131us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.380s 33.499us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.510s 1429.649us 1 1 100.00
lc_ctrl_tl_intg_err 3.100s 471.540us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.100s 471.540us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.190s 551.638us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.930s 247.594us 1 1 100.00
lc_ctrl_sec_cm 6.510s 1429.649us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.930s 247.594us 1 1 100.00
lc_ctrl_sec_cm 6.510s 1429.649us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.930s 247.594us 1 1 100.00
lc_ctrl_sec_cm 6.510s 1429.649us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.930s 247.594us 1 1 100.00
lc_ctrl_sec_cm 6.510s 1429.649us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.930s 247.594us 1 1 100.00
lc_ctrl_sec_cm 6.510s 1429.649us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.930s 247.594us 1 1 100.00
lc_ctrl_sec_cm 6.510s 1429.649us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.930s 247.594us 1 1 100.00
lc_ctrl_sec_cm 6.510s 1429.649us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.930s 247.594us 1 1 100.00
lc_ctrl_sec_cm 6.510s 1429.649us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 9.410s 467.012us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.880s 186.855us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.080s 365.069us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.770s 1541.864us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.770s 1541.864us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.640s 264.807us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.700s 878.731us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.700s 878.731us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 15.510s 639.422us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_scoreboard.sv:248) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* 1 test run
lc_ctrl_stress_all_with_rand_reset 37127622511816628503514175428788842249122232664457768264516664337572684574577 3878
UVM_INFO @ 639421563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---