Simulation Results: otbn

 
23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.95 %
  • code
  • 94.16 %
  • assert
  • 89.82 %
  • func
  • 97.88 %
  • block
  • 99.33 %
  • line
  • 99.49 %
  • branch
  • 91.59 %
  • toggle
  • 87.99 %
  • FSM
  • 97.56 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 73.611us 1 1 100.00
single_binary 1 1 100.00
otbn_single 11.000s 57.586us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 34.000s 44.279us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 34.000s 19.767us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 36.000s 293.765us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 34.000s 28.939us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 36.000s 33.172us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 34.000s 19.767us 1 1 100.00
otbn_csr_aliasing 34.000s 28.939us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 110.000s 5121.311us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 31.000s 304.239us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 25.000s 105.610us 1 1 100.00
multi_error 0 1 0.00
otbn_multi_err 26.000s 161.362us 0 1 0.00
back_to_back 1 1 100.00
otbn_multi 27.000s 89.429us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 44.000s 270.771us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 37.000s 298.938us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 4.000s 101.883us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 7.000s 71.976us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 34.000s 26.348us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 33.000s 15.767us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 206.571us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 206.571us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 34.000s 44.279us 1 1 100.00
otbn_csr_rw 34.000s 19.767us 1 1 100.00
otbn_csr_aliasing 34.000s 28.939us 1 1 100.00
otbn_same_csr_outstanding 3.000s 30.250us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 34.000s 44.279us 1 1 100.00
otbn_csr_rw 34.000s 19.767us 1 1 100.00
otbn_csr_aliasing 34.000s 28.939us 1 1 100.00
otbn_same_csr_outstanding 3.000s 30.250us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 36.000s 18.027us 1 1 100.00
otbn_dmem_err 41.000s 92.683us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 37.000s 18.326us 1 1 100.00
otbn_controller_ispr_rdata_err 37.000s 103.740us 1 1 100.00
otbn_mac_bignum_acc_err 30.000s 61.692us 1 1 100.00
otbn_urnd_err 4.000s 27.398us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 35.000s 22.419us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 23.000s 37.333us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 13.000s 26.968us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 113.000s 2729.010us 1 1 100.00
otbn_tl_intg_err 21.000s 253.334us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 22.000s 105.871us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 113.000s 2729.010us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 113.000s 2729.010us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 73.611us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 41.000s 92.683us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 36.000s 18.027us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 21.000s 253.334us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 37.000s 298.938us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 36.000s 18.027us 1 1 100.00
otbn_dmem_err 41.000s 92.683us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 101.883us 1 1 100.00
otbn_illegal_mem_acc 35.000s 22.419us 1 1 100.00
otbn_sec_cm 113.000s 2729.010us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 113.000s 2729.010us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 11.000s 57.586us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 36.000s 18.027us 1 1 100.00
otbn_dmem_err 41.000s 92.683us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 101.883us 1 1 100.00
otbn_illegal_mem_acc 35.000s 22.419us 1 1 100.00
otbn_sec_cm 113.000s 2729.010us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 113.000s 2729.010us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 37.000s 298.938us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 36.000s 18.027us 1 1 100.00
otbn_dmem_err 41.000s 92.683us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 101.883us 1 1 100.00
otbn_illegal_mem_acc 35.000s 22.419us 1 1 100.00
otbn_sec_cm 113.000s 2729.010us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 113.000s 2729.010us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 11.000s 57.586us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 36.000s 15.639us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 28.546us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 24.000s 221.451us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 24.000s 221.451us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 52.390us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 113.000s 2729.010us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 113.000s 2729.010us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 6.000s 916.321us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 113.000s 2729.010us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 113.000s 2729.010us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 12.000s 39.495us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 12.000s 39.495us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 24.597us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 11.000s 57.586us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 11.000s 57.586us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 11.000s 57.586us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 27.000s 89.429us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 11.000s 57.586us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 11.000s 57.586us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 19.000s 76.838us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 11.000s 57.586us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 113.000s 2729.010us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 4.000s 16.454us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 6.000s 70.002us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_multi_err 7038414173464919300460343325113186068940360768862929052281269664493590960730 296
UVM_INFO @ 161361678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 45822983059264456513310380144523878978127836727661197889604525004637380099422 147
UVM_INFO @ 16454081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---