Simulation Results: pwrmgr

 
23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.49 %
  • code
  • 97.33 %
  • assert
  • 97.13 %
  • func
  • 98.02 %
  • line
  • 99.09 %
  • branch
  • 96.18 %
  • cond
  • 95.76 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.570s 77.850us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.700s 28.729us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.680s 45.051us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.720s 346.183us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.890s 47.934us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.940s 52.236us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.680s 45.051us 1 1 100.00
pwrmgr_csr_aliasing 0.890s 47.934us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.580s 63.879us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.580s 63.879us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.720s 196.897us 1 1 100.00
pwrmgr_lowpower_invalid 0.620s 47.297us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.760s 60.260us 1 1 100.00
pwrmgr_reset_invalid 0.830s 104.779us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.760s 60.260us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.820s 150.016us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.900s 209.517us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.650s 197.992us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 3.090s 7199.315us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.590s 18.546us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.320s 92.652us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.320s 92.652us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.700s 28.729us 1 1 100.00
pwrmgr_csr_rw 0.680s 45.051us 1 1 100.00
pwrmgr_csr_aliasing 0.890s 47.934us 1 1 100.00
pwrmgr_same_csr_outstanding 0.700s 32.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.700s 28.729us 1 1 100.00
pwrmgr_csr_rw 0.680s 45.051us 1 1 100.00
pwrmgr_csr_aliasing 0.890s 47.934us 1 1 100.00
pwrmgr_same_csr_outstanding 0.700s 32.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 0.960s 132.719us 1 1 100.00
pwrmgr_sec_cm 1.240s 673.820us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.240s 673.820us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.240s 673.820us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 0.960s 132.719us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.980s 827.571us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.820s 150.016us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.400s 924.780us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.820s 130.397us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.670s 41.295us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.240s 673.820us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.240s 673.820us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.240s 673.820us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.560s 54.210us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.600s 49.624us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.100s 262.870us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.680s 45.051us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.680s 45.051us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.660s 355.907us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 8.200s 9390.870us 1 1 100.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 93776067863602916447300767939292539872131305737236936879321525452198722092324 79
UVM_ERROR @ 355907047 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 355907047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---