Simulation Results: rom_ctrl/32kb

 
23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.00 %
  • code
  • 96.98 %
  • assert
  • 96.66 %
  • func
  • 97.37 %
  • line
  • 99.46 %
  • branch
  • 98.91 %
  • cond
  • 97.77 %
  • toggle
  • 95.44 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.200s 136.275us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.730s 127.308us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.240s 224.242us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.760s 125.964us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.140s 299.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.030s 137.164us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.240s 224.242us 1 1 100.00
rom_ctrl_csr_aliasing 4.140s 299.000us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.900s 127.274us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.210s 385.503us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.740s 562.388us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 10.640s 1678.660us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 9.370s 822.965us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.390s 2517.933us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.650s 176.457us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.650s 176.457us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.730s 127.308us 1 1 100.00
rom_ctrl_csr_rw 3.240s 224.242us 1 1 100.00
rom_ctrl_csr_aliasing 4.140s 299.000us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.430s 126.972us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.730s 127.308us 1 1 100.00
rom_ctrl_csr_rw 3.240s 224.242us 1 1 100.00
rom_ctrl_csr_aliasing 4.140s 299.000us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.430s 126.972us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.560s 1691.169us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.760s 409.869us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 210.320s 1689.201us 1 1 100.00
rom_ctrl_tl_intg_err 44.240s 1118.417us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 210.320s 1689.201us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 210.320s 1689.201us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.560s 1691.169us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.560s 1691.169us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.560s 1691.169us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.560s 1691.169us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.560s 1691.169us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 210.320s 1689.201us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 210.320s 1689.201us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.200s 136.275us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.200s 136.275us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.200s 136.275us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 44.240s 1118.417us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.560s 1691.169us 1 1 100.00
rom_ctrl_kmac_err_chk 9.370s 822.965us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.560s 1691.169us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.560s 1691.169us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.560s 1691.169us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.760s 409.869us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 210.320s 1689.201us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 292.500s 6253.735us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 68519956963550593810051279082272550280890709413625308783799879007043217008036 79
UVM_INFO @ 562387569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---