Simulation Results: rom_ctrl/64kb

 
23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.11 %
  • code
  • 95.28 %
  • assert
  • 97.10 %
  • func
  • 95.94 %
  • line
  • 99.19 %
  • branch
  • 98.54 %
  • cond
  • 97.03 %
  • toggle
  • 94.96 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 8.330s 303.122us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 10.540s 717.157us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.530s 789.027us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 8.830s 1031.429us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 8.880s 1022.706us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.170s 399.628us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.530s 789.027us 1 1 100.00
rom_ctrl_csr_aliasing 8.880s 1022.706us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.450s 1155.819us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.750s 370.634us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 6.260s 174.141us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 26.610s 765.104us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.060s 2021.212us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.610s 2087.762us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 9.800s 2034.629us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 9.800s 2034.629us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.540s 717.157us 1 1 100.00
rom_ctrl_csr_rw 5.530s 789.027us 1 1 100.00
rom_ctrl_csr_aliasing 8.880s 1022.706us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.780s 864.558us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.540s 717.157us 1 1 100.00
rom_ctrl_csr_rw 5.530s 789.027us 1 1 100.00
rom_ctrl_csr_aliasing 8.880s 1022.706us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.780s 864.558us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 114.620s 45947.753us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 23.870s 2893.099us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 460.700s 1104.986us 1 1 100.00
rom_ctrl_tl_intg_err 52.070s 1258.832us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 460.700s 1104.986us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 460.700s 1104.986us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 114.620s 45947.753us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 114.620s 45947.753us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 114.620s 45947.753us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 114.620s 45947.753us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 114.620s 45947.753us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 460.700s 1104.986us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 460.700s 1104.986us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 8.330s 303.122us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 8.330s 303.122us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 8.330s 303.122us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 52.070s 1258.832us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 114.620s 45947.753us 1 1 100.00
rom_ctrl_kmac_err_chk 14.060s 2021.212us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 114.620s 45947.753us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 114.620s 45947.753us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 114.620s 45947.753us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 23.870s 2893.099us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 460.700s 1104.986us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 165.220s 6542.173us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 11306548990564389800070213682449558552619537323235018391771737266804385554889 79
UVM_INFO @ 174140511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---