Simulation Results: rstmgr

 
23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.28 %
  • code
  • 99.31 %
  • assert
  • 98.53 %
  • func
  • 97.01 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.75 %
  • toggle
  • 99.16 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.180s 139.524us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.810s 129.823us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.920s 82.655us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.700s 702.660us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 2.140s 418.002us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.840s 103.234us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.920s 82.655us 1 1 100.00
rstmgr_csr_aliasing 2.140s 418.002us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.830s 168.866us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.900s 417.026us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.820s 118.695us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.620s 1787.173us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.620s 1787.173us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.620s 1787.173us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.620s 1787.173us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 25.260s 11825.746us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.760s 76.860us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.030s 376.456us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.030s 376.456us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.810s 129.823us 1 1 100.00
rstmgr_csr_rw 0.920s 82.655us 1 1 100.00
rstmgr_csr_aliasing 2.140s 418.002us 1 1 100.00
rstmgr_same_csr_outstanding 1.180s 132.568us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.810s 129.823us 1 1 100.00
rstmgr_csr_rw 0.920s 82.655us 1 1 100.00
rstmgr_csr_aliasing 2.140s 418.002us 1 1 100.00
rstmgr_same_csr_outstanding 1.180s 132.568us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 18.720s 17572.125us 1 1 100.00
rstmgr_tl_intg_err 1.710s 497.534us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 18.720s 17572.125us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 18.720s 17572.125us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.710s 497.534us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.070s 200.993us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.810s 1405.450us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.150s 303.734us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 18.720s 17572.125us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.920s 82.655us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.920s 82.655us 1 1 100.00