Simulation Results: rv_timer

 
23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.93 %
  • code
  • 100.00 %
  • assert
  • 98.09 %
  • func
  • 89.71 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.230s 1000.333us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.630s 12.351us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.810s 37.084us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.880s 1537.613us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.690s 13.548us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.760s 27.621us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.810s 37.084us 1 1 100.00
rv_timer_csr_aliasing 0.690s 13.548us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.510s 575.496us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.410s 3704.106us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 70.100s 234075.901us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 70.100s 234075.901us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.920s 12360.460us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.570s 16.212us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.620s 35.341us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.320s 800.191us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.320s 800.191us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.630s 12.351us 1 1 100.00
rv_timer_csr_rw 0.810s 37.084us 1 1 100.00
rv_timer_csr_aliasing 0.690s 13.548us 1 1 100.00
rv_timer_same_csr_outstanding 0.620s 23.685us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.630s 12.351us 1 1 100.00
rv_timer_csr_rw 0.810s 37.084us 1 1 100.00
rv_timer_csr_aliasing 0.690s 13.548us 1 1 100.00
rv_timer_same_csr_outstanding 0.620s 23.685us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.750s 65.874us 1 1 100.00
rv_timer_tl_intg_err 0.730s 118.159us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.730s 118.159us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.760s 69.003us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.750s 177.079us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
rv_timer_stress_all_with_rand_reset 7.410s 5069.502us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 83338867420816898915152840541637375848224166271280941573442234495993813944033 77
UVM_INFO @ 69003437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 110808230379560278868086105482500720358335347952424074032493281714418251994271 76
UVM_INFO @ 575495593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 61183864359623766351063589918236975955932365668146955529118737233364661906325 75
UVM_INFO @ 177078526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) 1 test run
rv_timer_stress_all_with_rand_reset 53549526429318463698796472197284218486597885757862260488621102368565584691223 143
UVM_INFO @ 5069501983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---