Simulation Results: spi_device/1r1w

 
23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.08 %
  • code
  • 93.05 %
  • assert
  • 95.40 %
  • func
  • 63.79 %
  • line
  • 98.83 %
  • branch
  • 98.11 %
  • cond
  • 95.96 %
  • toggle
  • 83.01 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 11.770s 3522.524us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.960s 72.760us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.420s 38.105us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 25.630s 6562.004us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 4.080s 109.553us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.280s 112.776us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.420s 38.105us 1 1 100.00
spi_device_csr_aliasing 4.080s 109.553us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.640s 11.138us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.220s 303.856us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.840s 166.265us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.800s 2.399us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.760s 3.573us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.090s 96.720us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.090s 96.720us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 6.420s 1992.879us 1 1 100.00
spi_device_tpm_sts_read 0.820s 445.500us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 12.410s 30054.721us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 6.440s 23649.765us 1 1 100.00
spi_device_flash_all 54.580s 105332.020us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.420s 2455.831us 1 1 100.00
spi_device_flash_all 54.580s 105332.020us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.420s 2455.831us 1 1 100.00
spi_device_flash_all 54.580s 105332.020us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 54.580s 105332.020us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.810s 328.195us 1 1 100.00
spi_device_flash_all 54.580s 105332.020us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.810s 328.195us 1 1 100.00
spi_device_flash_all 54.580s 105332.020us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.810s 328.195us 1 1 100.00
spi_device_flash_all 54.580s 105332.020us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.810s 328.195us 1 1 100.00
spi_device_flash_all 54.580s 105332.020us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.810s 328.195us 1 1 100.00
spi_device_flash_all 54.580s 105332.020us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 1.620s 207.939us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 25.360s 14793.390us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 25.360s 14793.390us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 25.360s 14793.390us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 6.430s 1637.851us 1 1 100.00
spi_device_read_buffer_direct 7.040s 849.794us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 25.360s 14793.390us 1 1 100.00
spi_device_flash_all 54.580s 105332.020us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 54.580s 105332.020us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 54.580s 105332.020us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.500s 143.620us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.500s 143.620us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 143.320s 113497.722us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 11.770s 3522.524us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 3.110s 757.706us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 113.210s 43448.542us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.740s 118.957us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.810s 22.923us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.170s 41.804us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.170s 41.804us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.960s 72.760us 1 1 100.00
spi_device_csr_rw 1.420s 38.105us 1 1 100.00
spi_device_csr_aliasing 4.080s 109.553us 1 1 100.00
spi_device_same_csr_outstanding 2.730s 305.007us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.960s 72.760us 1 1 100.00
spi_device_csr_rw 1.420s 38.105us 1 1 100.00
spi_device_csr_aliasing 4.080s 109.553us 1 1 100.00
spi_device_same_csr_outstanding 2.730s 305.007us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.060s 425.667us 1 1 100.00
spi_device_tl_intg_err 5.470s 463.621us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 5.470s 463.621us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 77839664057741045997783061791234224546850763102955018340852971888704964122167 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1813523 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1813523 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[952])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 20369044892139247045598758934512553292141737305239426501432630295423205341014 76
UVM_ERROR @ 1662256 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x179b60 [101111001101101100000] vs 0x0 [0])
UVM_ERROR @ 1699256 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2125ff [1000010010010111111111] vs 0x0 [0])
UVM_ERROR @ 1771256 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd75d61 [110101110101110101100001] vs 0x0 [0])
UVM_ERROR @ 1783256 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2945e9 [1010010100010111101001] vs 0x0 [0])