Simulation Results: spi_host

 
23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.22 %
  • code
  • 91.09 %
  • assert
  • 94.33 %
  • func
  • 88.24 %
  • block
  • 96.60 %
  • line
  • 98.76 %
  • branch
  • 92.55 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 4.000s 734.221us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 47.306us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 16.510us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 4.000s 295.081us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 58.374us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 42.693us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 16.510us 1 1 100.00
spi_host_csr_aliasing 1.000s 58.374us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 16.303us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 67.727us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 57.000us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 110.389us 1 1 100.00
spi_host_error_cmd 1.000s 68.924us 1 1 100.00
spi_host_event 5.000s 6508.579us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 61.712us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 61.712us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 61.712us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 151.000s 5846.767us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 3.000s 279.027us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 25.309us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 61.712us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 61.712us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 4.000s 734.221us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 4.000s 734.221us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 29.000s 2541.553us 1 1 100.00
spien 1 1 100.00
spi_host_spien 10.000s 1994.824us 1 1 100.00
stall 0 1 0.00
spi_host_status_stall 21.000s 11670.151us 0 1 0.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 116.784us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 110.389us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 54.519us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 30.448us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 1.000s 220.043us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 1.000s 220.043us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 47.306us 1 1 100.00
spi_host_csr_rw 1.000s 16.510us 1 1 100.00
spi_host_csr_aliasing 1.000s 58.374us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 27.265us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 47.306us 1 1 100.00
spi_host_csr_rw 1.000s 16.510us 1 1 100.00
spi_host_csr_aliasing 1.000s 58.374us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 27.265us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 1.000s 62.238us 1 1 100.00
spi_host_sec_cm 2.000s 40.237us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 62.238us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* 1 test run
spi_host_status_stall 111616877523491672409341558995710430484190387492288676143716471838813321795663 916
UVM_INFO @ 11670150929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---