Simulation Results: sram_ctrl/main

 
23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.39 %
  • code
  • 94.75 %
  • assert
  • 97.82 %
  • func
  • 93.60 %
  • block
  • 94.96 %
  • line
  • 95.50 %
  • branch
  • 91.91 %
  • toggle
  • 91.60 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 3505.253us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 34.787us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 74.195us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 226.977us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 34.007us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 1431.613us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 74.195us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 34.007us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 92.000s 6182.610us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 41.000s 1385.262us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 7.000s 1525.221us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 124.000s 17116.114us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 121.000s 17075.283us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 35.000s 9163.161us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 14.000s 4949.152us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 29.000s 9092.942us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 754.107us 1 1 100.00
sram_ctrl_partial_access_b2b 224.000s 35677.973us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 3.000s 788.090us 0 1 0.00
sram_ctrl_throughput_w_partial_write 4.000s 2754.771us 0 1 0.00
sram_ctrl_throughput_w_readback 5.000s 9387.061us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 11.000s 2176.790us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 692.724us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 288.000s 241221.266us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 48.695us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 43.452us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 43.452us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 34.787us 1 1 100.00
sram_ctrl_csr_rw 1.000s 74.195us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 34.007us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 126.634us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 34.787us 1 1 100.00
sram_ctrl_csr_rw 1.000s 74.195us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 34.007us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 126.634us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 22.000s 20763.538us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 5716.678us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 105.091us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 5716.678us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 105.091us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 2176.790us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 11.000s 2176.790us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 74.195us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 29.000s 9092.942us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 29.000s 9092.942us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 29.000s 9092.942us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 14.000s 4949.152us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 5.000s 672.738us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 22.000s 20763.538us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 13292.794us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 3505.253us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 3505.253us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 29.000s 9092.942us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 5716.678us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 14.000s 4949.152us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 5716.678us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 5716.678us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 3505.253us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 5716.678us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 7.000s 363.315us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 30101864717264688745170285833506338990900220069376224152430042900477927043878 86
UVM_INFO @ 788089543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 47514805310967697787450062633767391285402880346750912937497222623285517698070 86
UVM_INFO @ 2754771392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 16311454722633300247371641741795464551387712795579551163929517327592734267082 86
UVM_INFO @ 9387060808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---