Simulation Results: sram_ctrl/ret

 
23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.37 %
  • code
  • 82.03 %
  • assert
  • 97.67 %
  • func
  • 94.40 %
  • block
  • 93.42 %
  • line
  • 94.39 %
  • branch
  • 88.73 %
  • toggle
  • 78.31 %
  • FSM
  • 66.67 %
Validation stages
V1
87.50%
V2
85.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 226.471us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 16.571us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 49.224us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 214.266us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 21.116us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 69.125us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 49.224us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 21.116us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 5.000s 1482.281us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 356.601us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 7.000s 300.511us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 150.000s 17313.762us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 5.000s 590.493us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 15.000s 2823.979us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 3.000s 927.552us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 9.000s 1196.517us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 105.911us 1 1 100.00
sram_ctrl_partial_access_b2b 283.000s 88787.244us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 2.000s 117.916us 0 1 0.00
sram_ctrl_throughput_w_partial_write 1.000s 77.936us 0 1 0.00
sram_ctrl_throughput_w_readback 1.000s 121.749us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 3.000s 67.508us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 29.060us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 18.000s 761.699us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 31.150us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 23.468us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 23.468us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 16.571us 1 1 100.00
sram_ctrl_csr_rw 1.000s 49.224us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 21.116us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 22.720us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 16.571us 1 1 100.00
sram_ctrl_csr_rw 1.000s 49.224us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 21.116us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 22.720us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 785.567us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 377.497us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 494.824us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 377.497us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 494.824us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 67.508us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 67.508us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 49.224us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 9.000s 1196.517us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 1196.517us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 1196.517us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 3.000s 927.552us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 53.721us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 785.567us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 50.544us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 226.471us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 226.471us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 9.000s 1196.517us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 377.497us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 3.000s 927.552us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 377.497us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 377.497us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 226.471us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 377.497us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
sram_ctrl_stress_all_with_rand_reset 27.000s 1515.858us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 100357039634739759674071928627806642399694458190078035089521249042548158097883 86
UVM_INFO @ 117915885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 103634326467296323981770117432437033164949853623364170356550454579180105176294 86
UVM_INFO @ 77935553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 69320905294668016985551497005473571939767954586559331433412547544771644511442 86
UVM_INFO @ 121749169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_driver.sv:148) [driver] Check failed seq_item_port.has_do_available() == * (* [*] vs * [*]) 1 test run
sram_ctrl_stress_all_with_rand_reset 48115138755313085617062150071196922465033581683545713771343428511713770812329 215
UVM_INFO @ 1515858026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 74988847717237617609201905076354132342080611086957551640994236630416155085892 94
UVM_INFO @ 69124730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---