Simulation Results: sysrst_ctrl

 
23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.17 %
  • code
  • 92.13 %
  • assert
  • 92.34 %
  • func
  • 65.03 %
  • line
  • 96.84 %
  • branch
  • 97.18 %
  • cond
  • 94.85 %
  • toggle
  • 100.00 %
  • FSM
  • 71.79 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.740s 2137.926us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 3.410s 2487.486us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 4.650s 2436.222us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 5.110s 2287.076us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 1.680s 6295.508us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 1.760s 2084.559us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 67.610s 38716.310us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 9.670s 3082.627us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 2.420s 2178.273us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 1.760s 2084.559us 1 1 100.00
sysrst_ctrl_csr_aliasing 9.670s 3082.627us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 13.840s 138714.186us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 40.050s 97704.464us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 175.650s 372753.400us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 2.300s 3484.244us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 4.470s 2510.759us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 5.090s 2022.778us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 4.600s 3330.089us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 2.950s 2618.473us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 4.390s 5198.761us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 28.560s 35254.324us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 26.620s 17180.671us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.930s 2030.011us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 4.910s 2014.004us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 3.770s 2201.635us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 3.770s 2201.635us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 1.680s 6295.508us 1 1 100.00
sysrst_ctrl_csr_rw 1.760s 2084.559us 1 1 100.00
sysrst_ctrl_csr_aliasing 9.670s 3082.627us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.640s 8094.982us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 1.680s 6295.508us 1 1 100.00
sysrst_ctrl_csr_rw 1.760s 2084.559us 1 1 100.00
sysrst_ctrl_csr_aliasing 9.670s 3082.627us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.640s 8094.982us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 34.870s 42070.466us 1 1 100.00
sysrst_ctrl_tl_intg_err 20.880s 42886.337us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 20.880s 42886.337us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 11.140s 22377.036us 1 1 100.00