Simulation Results: uart

 
23/06/2026 15:30:32 DVSim: v1.49.11 sha: fc79657 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.00 %
  • code
  • 95.96 %
  • assert
  • 97.12 %
  • func
  • 64.93 %
  • line
  • 99.17 %
  • branch
  • 96.97 %
  • cond
  • 96.15 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 11.020s 11061.464us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.550s 24.178us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.630s 21.951us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.420s 48.571us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.840s 49.735us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.780s 172.204us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.630s 21.951us 1 1 100.00
uart_csr_aliasing 0.840s 49.735us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 36.790s 50260.967us 1 1 100.00
parity 2 2 100.00
uart_smoke 11.020s 11061.464us 1 1 100.00
uart_tx_rx 36.790s 50260.967us 1 1 100.00
parity_error 2 2 100.00
uart_intr 10.050s 23075.482us 1 1 100.00
uart_rx_parity_err 28.760s 141270.613us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 36.790s 50260.967us 1 1 100.00
uart_intr 10.050s 23075.482us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 61.270s 59942.792us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 51.500s 212256.444us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 136.780s 150348.570us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 10.050s 23075.482us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 10.050s 23075.482us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 10.050s 23075.482us 1 1 100.00
perf 1 1 100.00
uart_perf 218.900s 16126.030us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 7.590s 8792.025us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 7.590s 8792.025us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 4.610s 16201.598us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 52.440s 70855.177us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.260s 1246.765us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 27.280s 5831.892us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 244.220s 68401.153us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 185.710s 282855.175us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.600s 14.947us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.650s 42.532us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.950s 542.794us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.950s 542.794us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.550s 24.178us 1 1 100.00
uart_csr_rw 0.630s 21.951us 1 1 100.00
uart_csr_aliasing 0.840s 49.735us 1 1 100.00
uart_same_csr_outstanding 0.740s 20.031us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.550s 24.178us 1 1 100.00
uart_csr_rw 0.630s 21.951us 1 1 100.00
uart_csr_aliasing 0.840s 49.735us 1 1 100.00
uart_same_csr_outstanding 0.740s 20.031us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.910s 38.447us 1 1 100.00
uart_tl_intg_err 0.890s 56.923us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.890s 56.923us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 18.700s 8033.764us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_noise_filter 17063290299009306873832650168408849752570879492362927277803053534087922318193 75
UVM_ERROR @ 10946277797 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 11395637797 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 11395757797 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (22 [0x16] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 11399717797 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0