Simulation Results: adc_ctrl

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.69 %
  • code
  • 92.47 %
  • assert
  • 91.90 %
  • func
  • 12.69 %
  • line
  • 98.03 %
  • branch
  • 96.29 %
  • cond
  • 85.69 %
  • toggle
  • 98.58 %
  • FSM
  • 83.78 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 1.610s 5718.223us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.080s 1234.478us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.820s 407.869us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 10.260s 46878.231us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.120s 962.629us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.090s 537.068us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.820s 407.869us 1 1 100.00
adc_ctrl_csr_aliasing 2.120s 962.629us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 0.650s 342.507us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 0.690s 316.638us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.890s 463.112us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.960s 518.297us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.690s 359.562us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.960s 513.806us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 0.820s 505.662us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 1.210s 468.228us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 3.780s 4658.152us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 10.300s 41740.221us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 137.080s 99205.957us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 8.300s 6512.867us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.670s 324.726us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.030s 344.487us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.920s 410.481us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.920s 410.481us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.080s 1234.478us 1 1 100.00
adc_ctrl_csr_rw 0.820s 407.869us 1 1 100.00
adc_ctrl_csr_aliasing 2.120s 962.629us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.510s 4315.954us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.080s 1234.478us 1 1 100.00
adc_ctrl_csr_rw 0.820s 407.869us 1 1 100.00
adc_ctrl_csr_aliasing 2.120s 962.629us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.510s 4315.954us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 3.220s 4576.018us 1 1 100.00
adc_ctrl_tl_intg_err 3.830s 4463.486us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 3.830s 4463.486us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 1.220s 1377.181us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 50783983588704621178465585592413440926482471633724201216520528891935267225608 386
UVM_INFO @ 342507274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 104341872843800440316306960111258199652742296549811006228033483054615114426481 386
UVM_INFO @ 316637963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 62150116263938835719471342721647280876875045258159827244566544145136581464792 386
UVM_INFO @ 463111701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 48901271996343528866027365825089311183811973148562751594040261021083794678872 386
UVM_INFO @ 518296681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 54743948845822057719091186973829252502043001104193988682786655658126293601662 386
UVM_INFO @ 359561955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 99479385886465572873012254532926257745402227271487015490463727733513200250558 386
UVM_INFO @ 513805659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 32989491484318791060589971184612362663219243387238077676553779818710400791563 386
UVM_INFO @ 468227702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 67809707379324979181940622118307433903546865856573663962023626457360267685326 386
UVM_INFO @ 505661947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 49482765697432947465080123816503621866965077112307350571368136266337433848205 423
UVM_INFO @ 1377180700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 8662407781364969258977357776994927621783804434611576655098585827414038280006 389
UVM_INFO @ 6512867495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---