Simulation Results: aes/masked

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.14 %
  • code
  • 93.66 %
  • assert
  • 98.23 %
  • func
  • 75.53 %
  • block
  • 94.38 %
  • line
  • 95.90 %
  • branch
  • 87.41 %
  • toggle
  • 97.99 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 76.589us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 77.604us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 100.681us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 82.272us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 833.392us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 369.194us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 114.224us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 82.272us 1 1 100.00
aes_csr_aliasing 2.000s 369.194us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 77.604us 1 1 100.00
aes_config_error 3.000s 74.475us 1 1 100.00
aes_stress 3.000s 95.414us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 77.604us 1 1 100.00
aes_config_error 3.000s 74.475us 1 1 100.00
aes_stress 3.000s 95.414us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 95.414us 1 1 100.00
aes_b2b 7.000s 371.307us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 95.414us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 77.604us 1 1 100.00
aes_config_error 3.000s 74.475us 1 1 100.00
aes_stress 3.000s 95.414us 1 1 100.00
aes_alert_reset 2.000s 62.669us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 76.163us 1 1 100.00
aes_config_error 3.000s 74.475us 1 1 100.00
aes_alert_reset 2.000s 62.669us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 7.000s 370.243us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 212.828us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 62.669us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 95.414us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 95.414us 1 1 100.00
aes_sideload 3.000s 158.940us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 199.744us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 23.000s 2226.266us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 75.162us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 257.487us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 257.487us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 100.681us 1 1 100.00
aes_csr_rw 1.000s 82.272us 1 1 100.00
aes_csr_aliasing 2.000s 369.194us 1 1 100.00
aes_same_csr_outstanding 2.000s 128.578us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 100.681us 1 1 100.00
aes_csr_rw 1.000s 82.272us 1 1 100.00
aes_csr_aliasing 2.000s 369.194us 1 1 100.00
aes_same_csr_outstanding 2.000s 128.578us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 194.901us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 5.000s 213.908us 0 1 0.00
aes_control_fi 2.000s 48.935us 1 1 100.00
aes_cipher_fi 2.000s 54.287us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 88.508us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 88.508us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 88.508us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 88.508us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 151.854us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 422.360us 1 1 100.00
aes_tl_intg_err 2.000s 536.385us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 536.385us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 62.669us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 88.508us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 88.508us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 77.604us 1 1 100.00
aes_stress 3.000s 95.414us 1 1 100.00
aes_alert_reset 2.000s 62.669us 1 1 100.00
aes_core_fi 3.000s 261.665us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 74.475us 1 1 100.00
aes_stress 3.000s 95.414us 1 1 100.00
aes_core_fi 3.000s 261.665us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 88.508us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 122.922us 1 1 100.00
aes_stress 3.000s 95.414us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 95.414us 1 1 100.00
aes_sideload 3.000s 158.940us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 122.922us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 122.922us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 122.922us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 122.922us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 122.922us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 95.414us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 95.414us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 5.000s 213.908us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 5.000s 213.908us 0 1 0.00
aes_control_fi 2.000s 48.935us 1 1 100.00
aes_cipher_fi 2.000s 54.287us 1 1 100.00
aes_ctr_fi 2.000s 64.330us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 5.000s 213.908us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 5.000s 213.908us 0 1 0.00
aes_control_fi 2.000s 48.935us 1 1 100.00
aes_cipher_fi 2.000s 54.287us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 54.287us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 5.000s 213.908us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 5.000s 213.908us 0 1 0.00
aes_control_fi 2.000s 48.935us 1 1 100.00
aes_ctr_fi 2.000s 64.330us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 5.000s 213.908us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 5.000s 213.908us 0 1 0.00
aes_control_fi 2.000s 48.935us 1 1 100.00
aes_cipher_fi 2.000s 54.287us 1 1 100.00
aes_ctr_fi 2.000s 64.330us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 62.669us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 5.000s 213.908us 0 1 0.00
aes_control_fi 2.000s 48.935us 1 1 100.00
aes_cipher_fi 2.000s 54.287us 1 1 100.00
aes_ctr_fi 2.000s 64.330us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 5.000s 213.908us 0 1 0.00
aes_control_fi 2.000s 48.935us 1 1 100.00
aes_cipher_fi 2.000s 54.287us 1 1 100.00
aes_ctr_fi 2.000s 64.330us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 5.000s 213.908us 0 1 0.00
aes_control_fi 2.000s 48.935us 1 1 100.00
aes_ctr_fi 2.000s 64.330us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 5.000s 213.908us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 5.000s 213.908us 0 1 0.00
aes_control_fi 2.000s 48.935us 1 1 100.00
aes_cipher_fi 2.000s 54.287us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 1.000s 16.544us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 19958967682836654062996101611338318144108783432370362137657193116468360094010 27143
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 105590648614558997126768294135887728916995711974063766933913261010338715294719 168
UVM_INFO @ 16544250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---