Simulation Results: alert_handler

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.47 %
  • code
  • 91.15 %
  • assert
  • 97.94 %
  • func
  • 82.32 %
  • line
  • 99.65 %
  • branch
  • 98.48 %
  • cond
  • 91.03 %
  • toggle
  • 92.38 %
  • FSM
  • 74.19 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 7.620s 106.486us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 6.170s 317.450us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 2.340s 44.851us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 80.100s 2471.030us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 80.380s 4263.498us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 6.070s 74.372us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 2.340s 44.851us 1 1 100.00
alert_handler_csr_aliasing 80.380s 4263.498us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 31.690s 645.602us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 15.090s 434.813us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1031.910s 85243.307us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 4.430s 75.783us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 7.620s 106.486us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 5.030s 77.066us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 9.330s 812.475us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 46.800s 1797.799us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 1546.480s 43615.481us 1 1 100.00
alert_handler_lpg_stub_clk 555.600s 44916.049us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 2792.590s 77468.129us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 4.430s 325.030us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.540s 193.020us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.280s 20.162us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 4.190s 156.374us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 4.190s 156.374us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 6.170s 317.450us 1 1 100.00
alert_handler_csr_rw 2.340s 44.851us 1 1 100.00
alert_handler_csr_aliasing 80.380s 4263.498us 1 1 100.00
alert_handler_same_csr_outstanding 6.660s 688.188us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 6.170s 317.450us 1 1 100.00
alert_handler_csr_rw 2.340s 44.851us 1 1 100.00
alert_handler_csr_aliasing 80.380s 4263.498us 1 1 100.00
alert_handler_same_csr_outstanding 6.660s 688.188us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 111.310s 9976.726us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 111.310s 9976.726us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 111.310s 9976.726us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 111.310s 9976.726us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 694.570s 66149.450us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 17.670s 2259.587us 1 1 100.00
alert_handler_tl_intg_err 26.650s 611.274us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 26.650s 611.274us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 111.310s 9976.726us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 7.620s 106.486us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 7.620s 106.486us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 7.620s 106.486us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 7.620s 106.486us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 4.430s 75.783us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1546.480s 43615.481us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 4.430s 75.783us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1031.910s 85243.307us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1031.910s 85243.307us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 17.670s 2259.587us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 17.670s 2259.587us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 17.670s 2259.587us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 17.670s 2259.587us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 17.670s 2259.587us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 17.670s 2259.587us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 17.670s 2259.587us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 17.670s 2259.587us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 17.670s 2259.587us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 47.910s 5334.752us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 78224474555659141470656536668312365211497968794729177048052419309144723288332 90
UVM_INFO @ 1797798939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 98211233158886393187899518764310297417079268253661552228691487595155552915188 192
UVM_INFO @ 325030499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 109420490187847334997573526475478225963875848142606456527680295969867987900105 104
UVM_INFO @ 5334752444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---