Simulation Results: chip

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 71.18 %
  • code
  • 84.45 %
  • assert
  • 97.49 %
  • func
  • 31.59 %
  • line
  • 94.35 %
  • branch
  • 93.74 %
  • cond
  • 88.52 %
  • toggle
  • 88.49 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
76.98%
V2S
100.00%
V3
69.23%
unmapped
63.64%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 182.340s 3479.606us 1 1 100.00
chip_sw_example_rom 82.630s 2570.323us 1 1 100.00
chip_sw_example_manufacturer 173.900s 3170.544us 1 1 100.00
chip_sw_example_concurrency 169.270s 3422.702us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 184.990s 4424.276us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 302.850s 4574.119us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 870.600s 11956.320us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 4869.400s 33386.852us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 57.590s 2501.886us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 4869.400s 33386.852us 1 1 100.00
chip_csr_rw 302.850s 4574.119us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 6.310s 179.691us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 287.410s 3989.159us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 287.410s 3989.159us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 287.410s 3989.159us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 357.220s 4155.177us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 357.220s 4155.177us 1 1 100.00
chip_sw_uart_tx_rx_idx1 339.350s 4696.576us 1 1 100.00
chip_sw_uart_tx_rx_idx2 425.480s 4286.365us 1 1 100.00
chip_sw_uart_tx_rx_idx3 367.780s 4777.792us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 1116.240s 8829.349us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1060.580s 8568.019us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 257.620s 3736.481us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 231.940s 4749.081us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 231.940s 4749.081us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 165.330s 3168.092us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 138.830s 3096.455us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 241.050s 4901.513us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 354.110s 6091.506us 1 1 100.00
chip_tap_straps_testunlock0 91.950s 3006.289us 1 1 100.00
chip_tap_straps_rma 212.370s 4513.528us 1 1 100.00
chip_tap_straps_prod 682.110s 9894.786us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 898.850s 9312.423us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 384.130s 5296.494us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 384.130s 5296.494us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 551.650s 7197.874us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 812.380s 10044.850us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 362.230s 4505.353us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 580.970s 6697.438us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3863.060s 19167.368us 1 1 100.00
chip_sw_aes_enc_jitter_en 217.860s 3877.423us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 664.620s 7026.054us 1 1 100.00
chip_sw_hmac_enc_jitter_en 177.230s 2764.942us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 909.990s 7706.370us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 214.840s 2615.635us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 319.070s 4255.447us 1 1 100.00
chip_sw_clkmgr_jitter 160.960s 3346.956us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 231.190s 3440.155us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 414.710s 5815.469us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 226.080s 5067.113us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 154.720s 2413.827us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 226.080s 5067.113us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 195.070s 3254.007us 1 1 100.00
chip_sw_aes_smoketest 220.360s 3459.724us 1 1 100.00
chip_sw_aon_timer_smoketest 162.850s 3540.504us 1 1 100.00
chip_sw_clkmgr_smoketest 171.280s 3833.305us 1 1 100.00
chip_sw_csrng_smoketest 134.940s 2605.531us 1 1 100.00
chip_sw_entropy_src_smoketest 1022.880s 7578.577us 1 1 100.00
chip_sw_gpio_smoketest 203.470s 3647.476us 1 1 100.00
chip_sw_hmac_smoketest 223.550s 3314.047us 1 1 100.00
chip_sw_kmac_smoketest 206.810s 2838.674us 1 1 100.00
chip_sw_otbn_smoketest 588.850s 5350.092us 1 1 100.00
chip_sw_pwrmgr_smoketest 306.150s 5951.174us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 255.780s 5462.392us 1 1 100.00
chip_sw_rv_plic_smoketest 133.820s 2386.894us 1 1 100.00
chip_sw_rv_timer_smoketest 179.090s 3343.497us 1 1 100.00
chip_sw_rstmgr_smoketest 174.400s 2447.951us 1 1 100.00
chip_sw_sram_ctrl_smoketest 160.920s 3333.673us 1 1 100.00
chip_sw_uart_smoketest 194.230s 3209.649us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 147.460s 2524.764us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 377.750s 5464.765us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 8190.330s 63890.369us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3145.140s 15501.408us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 30.978s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 215.360s 3447.044us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 188.510s 3123.864us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7514.140s 55359.720us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7624.370s 58337.750us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 76.080s 2616.700us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 76.080s 2616.700us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 4869.400s 33386.852us 1 1 100.00
chip_same_csr_outstanding 1451.170s 14929.046us 1 1 100.00
chip_csr_hw_reset 184.990s 4424.276us 1 1 100.00
chip_csr_rw 302.850s 4574.119us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 4869.400s 33386.852us 1 1 100.00
chip_same_csr_outstanding 1451.170s 14929.046us 1 1 100.00
chip_csr_hw_reset 184.990s 4424.276us 1 1 100.00
chip_csr_rw 302.850s 4574.119us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 54.710s 2623.908us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 5.630s 53.099us 1 1 100.00
xbar_smoke_large_delays 48.250s 8428.670us 1 1 100.00
xbar_smoke_slow_rsp 42.710s 4703.950us 1 1 100.00
xbar_random_zero_delays 16.380s 223.089us 1 1 100.00
xbar_random_large_delays 163.780s 29280.272us 1 1 100.00
xbar_random_slow_rsp 62.530s 7251.706us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 28.500s 975.644us 1 1 100.00
xbar_error_and_unmapped_addr 6.860s 81.242us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 16.050s 372.369us 1 1 100.00
xbar_error_and_unmapped_addr 6.860s 81.242us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 46.990s 2160.704us 1 1 100.00
xbar_access_same_device_slow_rsp 230.390s 28731.892us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 32.670s 576.694us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 74.790s 1184.555us 1 1 100.00
xbar_stress_all_with_error 69.040s 3479.955us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 96.930s 244.932us 1 1 100.00
xbar_stress_all_with_reset_error 22.980s 119.033us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3145.140s 15501.408us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2454.870s 27860.758us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 3075.630s 14844.419us 1 1 100.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 52.360s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 44.047s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 38.117s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 21.563s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 21.040s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 55.299s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 9.059s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 10.408s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 18.207s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 17.629s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 141.414s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 106.920s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 146.803s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 99.889s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 73.202s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 18.320s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 30.160s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 26.320s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 19.840s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 19.210s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 19.540s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 21.130s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 18.270s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 18.790s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 18.370s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 20.510s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 19.430s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 20.680s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 22.310s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 20.020s 10.360us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 59.120s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 86.317s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 92.630s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 74.212s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 76.188s 0.000us 0 1 0.00
rom_e2e_keymgr_init 3 3 100.00
rom_e2e_keymgr_init_rom_ext_meas 6158.140s 28433.538us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 6151.390s 29359.136us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 6233.880s 29999.043us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3346.210s 15648.561us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2969.120s 35213.945us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2969.120s 35213.945us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 161.410s 3228.896us 1 1 100.00
chip_sw_aes_enc_jitter_en 217.860s 3877.423us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 154.080s 2812.286us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 160.370s 3410.309us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 759.710s 8099.552us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 186.870s 3196.751us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 351.170s 5496.755us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 474.180s 5718.185us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 560.180s 5272.472us 1 1 100.00
chip_plic_all_irqs_10 325.590s 4458.548us 1 1 100.00
chip_plic_all_irqs_20 421.240s 4681.562us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 206.480s 3074.956us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1076.080s 11155.011us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 307.680s 4905.144us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 144.040s 2730.424us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.157s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1050.040s 8040.775us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1247.240s 8942.446us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 851.820s 7685.562us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8087.860s 255393.932us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 263.870s 4123.002us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 306.150s 5951.174us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 263.870s 4123.002us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 608.480s 9331.634us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 608.480s 9331.634us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 273.580s 7116.616us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 407.700s 4970.742us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 644.650s 6278.727us 1 1 100.00
chip_sw_aes_idle 160.370s 3410.309us 1 1 100.00
chip_sw_hmac_enc_idle 153.090s 2834.086us 1 1 100.00
chip_sw_kmac_idle 150.450s 2386.335us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 230.660s 3967.505us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 206.230s 4440.765us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 383.700s 4792.930us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 234.770s 4881.367us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 706.830s 11312.427us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 388.810s 4763.952us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 351.250s 4420.991us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 419.770s 4437.755us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 408.750s 4430.451us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 394.850s 4285.394us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 345.900s 5393.151us 1 1 100.00
chip_sw_ast_clk_outputs 551.650s 7197.874us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 356.390s 6923.048us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 419.770s 4437.755us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 408.750s 4430.451us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 362.230s 4505.353us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 580.970s 6697.438us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3863.060s 19167.368us 1 1 100.00
chip_sw_aes_enc_jitter_en 217.860s 3877.423us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 664.620s 7026.054us 1 1 100.00
chip_sw_hmac_enc_jitter_en 177.230s 2764.942us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 909.990s 7706.370us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 214.840s 2615.635us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 319.070s 4255.447us 1 1 100.00
chip_sw_clkmgr_jitter 160.960s 3346.956us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 136.000s 2810.026us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 403.590s 4777.593us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 629.640s 6986.195us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4251.070s 25428.176us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 188.250s 3105.359us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 155.930s 2851.298us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 704.960s 7265.583us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 182.050s 3469.661us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 388.060s 5070.931us 1 1 100.00
chip_sw_flash_init_reduced_freq 1295.530s 23262.780us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 11841.170s 129317.804us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 551.650s 7197.874us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 377.360s 4306.279us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 238.130s 3807.517us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 474.180s 5718.185us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1050.040s 8040.775us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2134.820s 24777.390us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 246.260s 5362.353us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 578.970s 7354.603us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 165.280s 2921.848us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 3556.800s 20772.407us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 158.680s 2672.940us 1 1 100.00
chip_sw_edn_entropy_reqs 608.740s 5449.699us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 158.680s 2672.940us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2134.820s 24777.390us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 143.210s 2861.047us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1250.740s 19085.441us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 608.040s 5443.964us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 580.970s 6697.438us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 333.520s 4046.617us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 362.230s 4505.353us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3752.950s 43518.311us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1250.740s 19085.441us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 211.870s 3293.236us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1598.830s 13117.732us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 152.780s 3036.135us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3752.950s 43518.311us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 152.780s 3036.135us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 152.780s 3036.135us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 152.780s 3036.135us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 152.780s 3036.135us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 474.180s 5718.185us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 184.440s 7148.667us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 556.710s 5532.980us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 477.930s 6301.844us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 477.930s 6301.844us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 246.950s 3511.790us 1 1 100.00
chip_sw_hmac_enc_jitter_en 177.230s 2764.942us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 153.090s 2834.086us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1012.210s 7981.280us 1 1 100.00
chip_sw_hmac_multistream_mode 0 1 0.00
chip_sw_hmac_multistream 1533.850s 12027.019us 0 1 0.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 376.090s 4529.317us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 452.490s 5200.061us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 515.700s 5821.935us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 345.730s 4308.832us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1598.830s 13117.732us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 909.990s 7706.370us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 762.230s 6490.656us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 759.710s 8099.552us 1 1 100.00
chip_sw_keymgr_sideload_otbn 0 1 0.00
chip_sw_keymgr_sideload_otbn 4875.480s 20018.488us 0 1 0.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 142.460s 3129.993us 1 1 100.00
chip_sw_kmac_mode_kmac 218.100s 3711.969us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 214.840s 2615.635us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1598.830s 13117.732us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 778.460s 13745.338us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 125.310s 2785.445us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1315.270s 10165.159us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 150.450s 2386.335us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 351.170s 5496.755us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 354.110s 6091.506us 1 1 100.00
chip_tap_straps_rma 212.370s 4513.528us 1 1 100.00
chip_tap_straps_prod 682.110s 9894.786us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 177.160s 3350.067us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 778.460s 13745.338us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 778.460s 13745.338us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 778.460s 13745.338us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1658.850s 13431.939us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 152.780s 3036.135us 0 1 0.00
chip_sw_flash_rma_unlocked 3752.950s 43518.311us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 221.970s 3916.426us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 505.820s 6870.727us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 663.200s 8036.110us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 446.730s 5508.963us 0 1 0.00
chip_sw_lc_ctrl_transition 778.460s 13745.338us 1 1 100.00
chip_sw_keymgr_key_derivation 1598.830s 13117.732us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 360.810s 10200.798us 1 1 100.00
chip_sw_sram_ctrl_execution_main 542.020s 8721.235us 1 1 100.00
chip_prim_tl_access 184.440s 7148.667us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 356.390s 6923.048us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 388.810s 4763.952us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 351.250s 4420.991us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 419.770s 4437.755us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 408.750s 4430.451us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 394.850s 4285.394us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 345.900s 5393.151us 1 1 100.00
chip_tap_straps_dev 354.110s 6091.506us 1 1 100.00
chip_tap_straps_rma 212.370s 4513.528us 1 1 100.00
chip_tap_straps_prod 682.110s 9894.786us 1 1 100.00
chip_rv_dm_lc_disabled 148.730s 4526.678us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 210.130s 3515.188us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 107.700s 3680.705us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 88.110s 3245.940us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 187.750s 3224.808us 1 1 100.00
chip_lc_test_locked 0 2 0.00
chip_sw_lc_walkthrough_testunlocks 594.710s 11208.748us 0 1 0.00
chip_rv_dm_lc_disabled 148.730s 4526.678us 0 1 0.00
chip_sw_lc_walkthrough 1 5 20.00
chip_sw_lc_walkthrough_dev 757.790s 12792.406us 0 1 0.00
chip_sw_lc_walkthrough_prod 731.460s 11809.567us 0 1 0.00
chip_sw_lc_walkthrough_prodend 642.140s 8824.505us 1 1 100.00
chip_sw_lc_walkthrough_rma 358.670s 7888.829us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 594.710s 11208.748us 0 1 0.00
chip_sw_lc_ctrl_volatile_raw_unlock 1 3 33.33
chip_sw_lc_ctrl_volatile_raw_unlock 66.990s 2024.212us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 773.790s 26214.136us 0 1 0.00
rom_volatile_raw_unlock 102.962s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3797.220s 17334.405us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3863.060s 19167.368us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 644.650s 6278.727us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 644.650s 6278.727us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 644.650s 6278.727us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 330.450s 4481.885us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 778.460s 13745.338us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1250.740s 19085.441us 1 1 100.00
chip_sw_otbn_mem_scramble 330.450s 4481.885us 1 1 100.00
chip_sw_keymgr_key_derivation 1598.830s 13117.732us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 329.860s 4350.095us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 149.190s 2814.437us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1250.740s 19085.441us 1 1 100.00
chip_sw_otbn_mem_scramble 330.450s 4481.885us 1 1 100.00
chip_sw_keymgr_key_derivation 1598.830s 13117.732us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 329.860s 4350.095us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 149.190s 2814.437us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 778.460s 13745.338us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 310.240s 5369.658us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 177.160s 3350.067us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 221.970s 3916.426us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 505.820s 6870.727us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 663.200s 8036.110us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 446.730s 5508.963us 0 1 0.00
chip_sw_lc_ctrl_transition 778.460s 13745.338us 1 1 100.00
chip_prim_tl_access 184.440s 7148.667us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 184.440s 7148.667us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 840.610s 7056.413us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 62.100s 2143.672us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1173.750s 23359.680us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 262.410s 7219.390us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 297.190s 7202.533us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 399.400s 7451.064us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1039.220s 22227.563us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1 2 50.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 257.100s 5700.062us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 608.480s 9331.634us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 787.860s 11093.561us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 293.560s 4857.964us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 62.100s 2143.672us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 333.690s 4602.819us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 755.880s 11399.850us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 291.860s 6380.627us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 141.930s 3036.932us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 537.150s 13646.506us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 639.940s 7691.128us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 812.610s 10107.441us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1730.340s 29017.666us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 160.660s 3059.236us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 474.180s 5718.185us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 360.810s 10200.798us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 360.810s 10200.798us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 812.610s 10107.441us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 537.150s 13646.506us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 293.560s 4857.964us 1 1 100.00
chip_sw_pwrmgr_smoketest 306.150s 5951.174us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 359.510s 5328.319us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 351.310s 6603.856us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 313.050s 4516.776us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1076.080s 11155.011us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 119.520s 2883.525us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 474.180s 5718.185us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1247.240s 8942.446us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 546.890s 4994.875us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 519.610s 4361.809us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 195.120s 2847.140us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 149.190s 2814.437us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 351.310s 6603.856us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 351.310s 6603.856us 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 120.040s 2119.213us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 1152.400s 15906.480us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 986.530s 13825.927us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 359.510s 5328.319us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 233.820s 3418.988us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 330.550s 5801.444us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 212.370s 4513.528us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 148.730s 4526.678us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 560.180s 5272.472us 1 1 100.00
chip_plic_all_irqs_10 325.590s 4458.548us 1 1 100.00
chip_plic_all_irqs_20 421.240s 4681.562us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 175.000s 3529.463us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 172.910s 3341.658us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3145.140s 15501.408us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 247.640s 3471.088us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 217.030s 3426.498us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 197.440s 3913.244us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 198.640s 3246.540us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 329.860s 4350.095us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 319.070s 4255.447us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 554.660s 9546.205us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 472.500s 8554.511us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 542.020s 8721.235us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 474.180s 5718.185us 1 1 100.00
chip_sw_data_integrity_escalation 384.130s 5296.494us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 639.940s 7691.128us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1096.090s 23622.125us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 167.860s 2872.829us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 258.630s 3446.129us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 394.990s 5551.838us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1096.090s 23622.125us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1096.090s 23622.125us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2456.390s 20502.204us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2456.390s 20502.204us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 334.330s 6601.214us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2969.120s 35213.945us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 145.160s 2494.172us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 147.970s 2560.386us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 349.060s 4214.077us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 333.600s 4163.472us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1018.950s 8677.101us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5573.290s 31512.804us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1903.660s 12327.754us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 154.000s 2820.303us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 201.880s 3808.577us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 99.430s 2697.095us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9921.580s 72041.456us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1140.570s 7000.130us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 169.260s 4597.490us 0 1 0.00
rom_e2e_jtag_debug_dev 600.190s 15369.292us 0 1 0.00
rom_e2e_jtag_debug_rma 203.020s 4261.550us 0 1 0.00
rom_e2e_jtag_inject 1 3 33.33
rom_e2e_jtag_inject_test_unlocked0 60.120s 2220.325us 0 1 0.00
rom_e2e_jtag_inject_dev 300.390s 6171.131us 1 1 100.00
rom_e2e_jtag_inject_rma 62.990s 2477.187us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 48.427s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 277.350s 3622.275us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 400.430s 3352.320us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 497.830s 3951.852us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 967.550s 7871.328us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 244.120s 2212.028us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 637.530s 5696.069us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 169.550s 3017.773us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 180.510s 3593.843us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 249.210s 6237.970us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 259.780s 5022.135us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 812.610s 10107.441us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 169.260s 4597.490us 0 1 0.00
rom_e2e_jtag_debug_dev 600.190s 15369.292us 0 1 0.00
rom_e2e_jtag_debug_rma 203.020s 4261.550us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 420.270s 6085.464us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 474.180s 5718.185us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5890.950s 38314.732us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5890.950s 38314.732us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 185.780s 3819.263us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 357.220s 4155.177us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3127.750s 19337.177us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 7 11 63.64
chip_sival_flash_info_access 252.550s 3581.798us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 19.020s 10.400us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 5.480s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 182.010s 3210.465us 1 1 100.00
chip_sw_otp_ctrl_descrambling 172.240s 3100.670us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 240.590s 3669.499us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 7.557s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 192.730s 2645.402us 1 1 100.00
ate_bootstrap_flash_erase 591.940s 10010.220us 0 1 0.00
ate_bootstrap_one_frame 6284.580s 45856.713us 1 1 100.00
ate_bootstrap_disjoint 10169.130s 83967.752us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 24 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 72635331768519915670720908549463653678964875486079149450868427410908456672176 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 83510513078715564513536782140251515260577697904901419488258274911224020705728 None
---- STDERR ----
Another command (pid=374300) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=442912) is running. Waiting for it to complete on the server (server_pid=281510)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 35905980146298683707438666176997933807818614573734880927598541167751634571091 None
Another command (pid=669258) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=671701) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=665647) is running. Waiting for it to complete on the server (server_pid=281510)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 52321245647023472926502716790872547826881745947942419658863263086145956322446 None
Another command (pid=597706) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=598721) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=641352) is running. Waiting for it to complete on the server (server_pid=281510)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 97447652723220116009555974519370351940479073429368972181159165818801298043299 None
Another command (pid=607849) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=603452) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=604344) is running. Waiting for it to complete on the server (server_pid=281510)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 59635515950207275648889377904506793939728489544167415108316121701728542847890 None
Another command (pid=543334) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=625119) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=607849) is running. Waiting for it to complete on the server (server_pid=281510)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 45413367600905918468269837241725436026924272424553865825035531509057115275310 None
---- STDERR ----
Another command (pid=374300) is running. Waiting for it to complete on the server (server_pid=281510)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 54648098571120024513314025124196360693707188520397950140393930655296796802215 None
---- STDERR ----
Another command (pid=566075) is running. Waiting for it to complete on the server (server_pid=281510)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 85163152477638437705900048282842664844000715953296351319265924804833864966786 None
Another command (pid=465626) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=555638) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=459916) is running. Waiting for it to complete on the server (server_pid=281510)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 110406115054876696723995306105319191512881378327232242154875276157070793742075 None
Another command (pid=584889) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=592722) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=600386) is running. Waiting for it to complete on the server (server_pid=281510)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 12881128794640548536880488104022748329300555952393067395458139084100581621548 None
Another command (pid=584889) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=592722) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=600386) is running. Waiting for it to complete on the server (server_pid=281510)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 21167117569129693469541893799377332781599394038095673128267162714546428286371 None
Another command (pid=570344) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=566075) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=375880) is running. Waiting for it to complete on the server (server_pid=281510)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 77420239028285039784698366483946214605063939656516982144364041601479244211898 None
Another command (pid=607849) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=603452) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=604344) is running. Waiting for it to complete on the server (server_pid=281510)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 86064967466522372179099413284890862151496491694514415867405954527862510912144 None
Another command (pid=697433) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=623583) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=694201) is running. Waiting for it to complete on the server (server_pid=281510)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 83809247702740570457770397826363810211158281418754796014749389885750811882060 None
Another command (pid=650170) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=597706) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=598721) is running. Waiting for it to complete on the server (server_pid=281510)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 85592434011839017340754881204410453010712348358250950986991462018897746156345 None
Another command (pid=597313) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=461573) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=653250) is running. Waiting for it to complete on the server (server_pid=281510)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 68349114468844642823319647322131129787684350086628300592639054750213497819935 None
---- STDERR ----
Another command (pid=374300) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=442912) is running. Waiting for it to complete on the server (server_pid=281510)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 38654608799258215453844927497147533545600257397583192224978872810832680323387 None
Another command (pid=578486) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=375880) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=555638) is running. Waiting for it to complete on the server (server_pid=281510)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 33888742103267333617271514298025420612169348751674607848858144715049226383680 None
Another command (pid=594290) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=593248) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=584889) is running. Waiting for it to complete on the server (server_pid=281510)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 5207315747982441565775587691811615206289628169059860558445250656434201853393 None
Another command (pid=428422) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=450014) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=448892) is running. Waiting for it to complete on the server (server_pid=281510)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 17400906581687830521094749933080226998233193265605798923891414032779962749148 None
Another command (pid=450856) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=395315) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=451935) is running. Waiting for it to complete on the server (server_pid=281510)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 84795416364799278670507000503486398365832928689893468894852535494115770534151 None
Another command (pid=448892) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=461086) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=450856) is running. Waiting for it to complete on the server (server_pid=281510)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 29211897015943504235457856495380077864794546047846003087610429395383406026925 None
Another command (pid=374300) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=382956) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=442912) is running. Waiting for it to complete on the server (server_pid=281510)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 62464478462860950592649172466102332228671848597589729099400927359338733412115 None
Another command (pid=374300) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=442912) is running. Waiting for it to complete on the server (server_pid=281510)...
Another command (pid=379449) is running. Waiting for it to complete on the server (server_pid=281510)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 6 test runs
rom_e2e_sigverify_always_a_bad_b_bad_prod 108341999229099813640670310678645393405755883893359845442898424662015158324635 367
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 66553851847306303818413680703740967778442014425765066745439714819953776151802 368
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 26481339857873750501222021210851987504767491543318406892211983430207422198922 365
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 87273171406072614215215105399747963879978588724183256576847571670946152562453 327
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 49865316148975180436968750389324751012577450147069240497688531456330807009712 325
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 103216898972930485479534354483927181521364494363700514253495962113470094382805 326
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access 5 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 75669233549480847334855011905252373380874570886119027818698800159849229588567 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 45962416132967316356641739213065693815842951481537919766084010231257124547597 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 102406158554966521643672471712193328352694894448171818442751267725110268880797 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 56492942302265584746406954533205334451799379881747891378992251289564394751234 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 106587753063490023523577043686539755821541088980552316856523012813900968041499 307
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
Offending '(rstreqs[*] && (reset_cause == HwReq))' 4 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 57592394809959237038225911531371740372709173196059932251412114376035883241736 344
UVM_ERROR @ 13646.506000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 13646.506000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 65034344840644822288215919098303050158122415845709473854103522625890278499285 314
UVM_ERROR @ 5700.062500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5700.062500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 7534193502028299176369557640870574575115743830733670780524227835858890489028 325
UVM_ERROR @ 7202.532500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7202.532500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 90985389557248689871584761915740900966442753683348797605189987240722141950331 342
UVM_ERROR @ 11399.850000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 11399.850000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 88496735607761123444839720972511378226148302593309421316684562585482192129690 369
UVM_INFO @ 12792.406124 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 68404649461510639580750833067061173210017533677086261801846006408450752992791 369
UVM_INFO @ 11809.566504 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 82618214059400727983032399585922653751874936708899106090537375184680085106213 341
UVM_INFO @ 7888.829092 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 3 test runs
rom_e2e_sigverify_always_a_nothing_b_bad_prod 85795226728591925789739034635366230238065177903930260079956110858578473058179 325
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 90258780868163127020681504933130802136379944902714251799835079207249854996136 325
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 67313548349204425799056576902705598518490201828723397717451548877721573062439 327
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 2 test runs
chip_sw_lc_walkthrough_testunlocks 3825651285912622005375270616595774324100097351787308642448511806222190139023 364
UVM_ERROR @ 11208.748000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 11208.748000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_full_aon_reset 63126046316851178565283952806396785474240727048974854112167293469749152624539 303
UVM_ERROR @ 2143.672390 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 2143.672390 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 2 test runs
chip_sw_hmac_multistream 20057811403175817191086723827056874716714870541805470718720056501805170461849 345
UVM_INFO @ 12027.018878 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 92424339351198856399287764866160453582028932887334574499742290381047673480847 336
UVM_INFO @ 20018.487579 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 20894588397627483912765219597493629540565945181474523756416514855805153250352 217
TL item was: req: (cip_tl_seq_item@35746) { a_addr: 'h10358 a_data: 'h998d8c70 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h15 a_opcode: 'h4 a_user: 'h19237 d_param: 'h0 d_source: 'h15 d_data: 'h7b302573 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd1f a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2616.700408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 38163518641012334751867113571417313089518582673412314906979633558326180457851 224
TL item was: req: (cip_tl_seq_item@30978) { a_addr: 'h1070c a_data: 'hb848e2cf a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h31 a_opcode: 'h4 a_user: 'h181b7 d_param: 'h0 d_source: 'h31 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2501.886321 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 100430868691931497039381787716249388222178045795017649111572594202586143437023 362
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 5834978612621240129867254160853802771271404614128686122235526189654835927896 325
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_dev 30431115744626614231977656447026324415171640622677978476825409213582318839891 368
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 35474291542585406882750847442764146852097408139322166739699827681147514244345 328
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr_aon.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 1369674371051992765097329348894623045991381705202621708067566690098881889574 301
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 96776883050418593316772176302843807433082356253060451729281044701875522529192 327
UVM_INFO @ 3426.497896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 19475821025513302573717838931065491607746674786688352878512950726396813291477 309
UVM_INFO @ 3036.135486 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 47272969457184064495488332295724791083259710298700668621169420116735028476641 342
UVM_INFO @ 5508.963064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 1 test run
chip_sw_otp_ctrl_escalation 43118747515872071302755595945060618584968492826417630666579060979414331783969 316
UVM_ERROR @ 3593.843184 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3593.843184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 70000569507879635705369578796152236600020833976680580930044873044936330922165 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_volatile_raw_unlock_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 7197525078789815420032847634967572419417312147278383124789336105949125738280 309
UVM_INFO @ 26214.136373 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 1 test run
chip_sw_pwrmgr_sleep_power_glitch_reset 75697723999426994198191422191077398106515382102840885379735639113710464103770 313
UVM_ERROR @ 3036.931795 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3036.931795 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 7509012445639789208847368236688180481254113039415407273687967244267899624857 332
UVM_INFO @ 35213.944924 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:302)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 66305573334137099395056208348469847501768499252516775343707081729995116331258 307
UVM_INFO @ 3196.750571 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 79821322788484894926871576190838997289322728171354033036881524768118296645751 308
UVM_INFO @ 2730.424004 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 74890568418864466493055031882854439835596839982172128212578772690570298216356 None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 111016099808797649848835532757114234007027524631119167158885668163205341045368 343
UVM_INFO @ 3622.275329 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 104785327083314306079498958684229545999918024256644919185024212234637995842113 225
UVM_INFO @ 4526.677673 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_idle_load 87707508226954503073599665222593245893816214848750188168880794456647468627213 312
UVM_INFO @ 3447.044500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * 1 test run
chip_sw_power_sleep_load 93665533755119787301837225235523997571439053286950932738046977128904372854760 318
UVM_INFO @ 3123.864000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 34521168800610499225684202598300696313496026980208314232972483273037497945473 327
UVM_INFO @ 10044.849713 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 114134928096677728992261556595216432721826534440136638017945875632122821846178 272
UVM_INFO @ 10010.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 21841955495177680169937942096246664174365242448492068568837998647249948173924 326
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_dev 110494560210987716568978867460163749649236078497699382358886461780631655818883 325
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! 1 test run
rom_e2e_jtag_debug_dev 4949002838277629346745247607396338133255322783488834736885693433365649717852 330
UVM_INFO @ 15369.292427 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 81379337488864268178180942336164478988612964201328418599191169537816233970730 327
UVM_ERROR @ 5464.764510 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5464.764510 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---