Simulation Results: clkmgr

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.69 %
  • code
  • 97.84 %
  • assert
  • 94.63 %
  • func
  • 85.59 %
  • line
  • 98.93 %
  • branch
  • 98.64 %
  • cond
  • 92.45 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.080s 56.612us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.890s 18.700us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.860s 15.873us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 2.940s 238.464us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 2.940s 1030.521us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.840s 25.959us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.860s 15.873us 1 1 100.00
clkmgr_csr_aliasing 2.940s 1030.521us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.690s 22.681us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.030s 80.332us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.870s 21.837us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.770s 79.251us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.080s 56.612us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 6.870s 1398.015us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 5.480s 2165.005us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 6.870s 1398.015us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 3.150s 939.202us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.700s 23.877us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.610s 65.314us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.610s 65.314us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.890s 18.700us 1 1 100.00
clkmgr_csr_rw 0.860s 15.873us 1 1 100.00
clkmgr_csr_aliasing 2.940s 1030.521us 1 1 100.00
clkmgr_same_csr_outstanding 1.320s 165.183us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.890s 18.700us 1 1 100.00
clkmgr_csr_rw 0.860s 15.873us 1 1 100.00
clkmgr_csr_aliasing 2.940s 1030.521us 1 1 100.00
clkmgr_same_csr_outstanding 1.320s 165.183us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 1.120s 12.928us 0 1 0.00
clkmgr_tl_intg_err 2.420s 720.770us 1 1 100.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 531.970s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 531.970s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 531.970s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 531.970s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 1.570s 155.516us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.420s 720.770us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 6.870s 1398.015us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 5.480s 2165.005us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 531.970s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.820s 30.096us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.870s 86.829us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.720s 18.869us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 1.020s 157.973us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 1.140s 231.348us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.860s 15.873us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 1.120s 12.928us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.860s 15.873us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.860s 15.873us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 1.120s 12.928us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 4.090s 1453.210us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 29.150s 2748.352us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 107077499156052302327369911470019691918252821044156134631495574714628251627610 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 47012407385241775024505480005299459294164896506413624321602183683307893170079 84
UVM_INFO @ 12928036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---