Simulation Results: csrng

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.38 %
  • code
  • 92.43 %
  • assert
  • 94.98 %
  • func
  • 77.73 %
  • block
  • 97.09 %
  • line
  • 97.80 %
  • branch
  • 92.77 %
  • toggle
  • 93.44 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 85.973us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 1.000s 22.857us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 1.000s 15.320us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 27.000s 1595.198us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 5.000s 292.462us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 109.789us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 1.000s 15.320us 1 1 100.00
csrng_csr_aliasing 5.000s 292.462us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 6.000s 329.550us 1 1 100.00
alerts 1 1 100.00
csrng_alert 4.000s 53.776us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 26.553us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 2.000s 7.433us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 2.000s 7.433us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 411.000s 19488.555us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 74.006us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 24.869us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 4.000s 96.509us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 4.000s 96.509us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 1.000s 22.857us 1 1 100.00
csrng_csr_rw 1.000s 15.320us 1 1 100.00
csrng_csr_aliasing 5.000s 292.462us 1 1 100.00
csrng_same_csr_outstanding 2.000s 25.303us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 1.000s 22.857us 1 1 100.00
csrng_csr_rw 1.000s 15.320us 1 1 100.00
csrng_csr_aliasing 5.000s 292.462us 1 1 100.00
csrng_same_csr_outstanding 2.000s 25.303us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 78.029us 1 1 100.00
csrng_tl_intg_err 5.000s 125.214us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 1.000s 39.411us 1 1 100.00
csrng_csr_rw 1.000s 15.320us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 4.000s 53.776us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 411.000s 19488.555us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 6.000s 329.550us 1 1 100.00
csrng_err 2.000s 26.553us 1 1 100.00
csrng_sec_cm 3.000s 78.029us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 6.000s 329.550us 1 1 100.00
csrng_err 2.000s 26.553us 1 1 100.00
csrng_sec_cm 3.000s 78.029us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 6.000s 329.550us 1 1 100.00
csrng_err 2.000s 26.553us 1 1 100.00
csrng_sec_cm 3.000s 78.029us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 6.000s 329.550us 1 1 100.00
csrng_err 2.000s 26.553us 1 1 100.00
csrng_sec_cm 3.000s 78.029us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 6.000s 329.550us 1 1 100.00
csrng_err 2.000s 26.553us 1 1 100.00
csrng_sec_cm 3.000s 78.029us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 4.000s 53.776us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 6.000s 329.550us 1 1 100.00
csrng_err 2.000s 26.553us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 411.000s 19488.555us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 4.000s 53.776us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 5.000s 125.214us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 6.000s 329.550us 1 1 100.00
csrng_err 2.000s 26.553us 1 1 100.00
csrng_sec_cm 3.000s 78.029us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 6.000s 329.550us 1 1 100.00
csrng_err 2.000s 26.553us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 6.000s 329.550us 1 1 100.00
csrng_err 2.000s 26.553us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 6.000s 329.550us 1 1 100.00
csrng_err 2.000s 26.553us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 6.000s 329.550us 1 1 100.00
csrng_err 2.000s 26.553us 1 1 100.00
csrng_sec_cm 3.000s 78.029us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 6.000s 329.550us 1 1 100.00
csrng_err 2.000s 26.553us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3602.075s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 111289069404365323657018561921790768320218079002122438356858934737835791757763 100
UVM_INFO @ 7433079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 65408901035661920669766896073436465234268975686034203331435802528214623589988 None