Simulation Results: edn/edn0

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.20 %
  • code
  • 82.04 %
  • assert
  • 96.96 %
  • func
  • 73.61 %
  • line
  • 97.55 %
  • branch
  • 91.35 %
  • cond
  • 83.87 %
  • toggle
  • 83.11 %
  • FSM
  • 54.30 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.860s 17.768us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.890s 42.852us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.030s 138.700us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.250s 324.072us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.200s 67.150us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.080s 16.086us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.030s 138.700us 1 1 100.00
edn_csr_aliasing 1.200s 67.150us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.650s 163.614us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.650s 163.614us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.650s 163.614us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.980s 29.623us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.030s 22.963us 1 1 100.00
errs 1 1 100.00
edn_err 0.830s 33.377us 1 1 100.00
disable 2 2 100.00
edn_disable 0.960s 22.526us 1 1 100.00
edn_disable_auto_req_mode 1.030s 95.878us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.130s 83.090us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.970s 27.833us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.890s 21.586us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.010s 122.189us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.010s 122.189us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.890s 42.852us 1 1 100.00
edn_csr_rw 1.030s 138.700us 1 1 100.00
edn_csr_aliasing 1.200s 67.150us 1 1 100.00
edn_same_csr_outstanding 1.130s 20.759us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.890s 42.852us 1 1 100.00
edn_csr_rw 1.030s 138.700us 1 1 100.00
edn_csr_aliasing 1.200s 67.150us 1 1 100.00
edn_same_csr_outstanding 1.130s 20.759us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.400s 9119.869us 1 1 100.00
edn_tl_intg_err 1.220s 93.203us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.050s 80.022us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.030s 22.963us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.400s 9119.869us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.400s 9119.869us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.400s 9119.869us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.400s 9119.869us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.030s 22.963us 1 1 100.00
edn_sec_cm 7.400s 9119.869us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.030s 22.963us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.220s 93.203us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 56.530s 2459.133us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
edn_stress_all_with_rand_reset 108088115541703981109737079834254327834339757623415808841539558111737373785532 341
UVM_INFO @ 2459133166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---