Simulation Results: edn/edn1

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.73 %
  • code
  • 82.40 %
  • assert
  • 98.18 %
  • func
  • 79.62 %
  • line
  • 97.95 %
  • branch
  • 92.86 %
  • cond
  • 91.23 %
  • toggle
  • 87.93 %
  • FSM
  • 42.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.900s 30.841us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.770s 33.138us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.020s 17.004us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.660s 1702.076us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.960s 30.045us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.870s 24.403us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.020s 17.004us 1 1 100.00
edn_csr_aliasing 0.960s 30.045us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.020s 44.909us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.020s 44.909us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.020s 44.909us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.740s 35.721us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.860s 34.398us 1 1 100.00
errs 1 1 100.00
edn_err 0.920s 142.201us 1 1 100.00
disable 2 2 100.00
edn_disable 0.740s 21.110us 1 1 100.00
edn_disable_auto_req_mode 1.180s 32.759us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.970s 471.330us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.920s 94.871us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.860s 17.937us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.980s 114.428us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.980s 114.428us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.770s 33.138us 1 1 100.00
edn_csr_rw 1.020s 17.004us 1 1 100.00
edn_csr_aliasing 0.960s 30.045us 1 1 100.00
edn_same_csr_outstanding 0.900s 80.759us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.770s 33.138us 1 1 100.00
edn_csr_rw 1.020s 17.004us 1 1 100.00
edn_csr_aliasing 0.960s 30.045us 1 1 100.00
edn_same_csr_outstanding 0.900s 80.759us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.350s 209.451us 1 1 100.00
edn_tl_intg_err 1.290s 56.535us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.800s 55.219us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.860s 34.398us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.350s 209.451us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.350s 209.451us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.350s 209.451us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.350s 209.451us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.860s 34.398us 1 1 100.00
edn_sec_cm 2.350s 209.451us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.860s 34.398us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.290s 56.535us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 71.920s 8184.657us 1 1 100.00