Simulation Results: entropy_src/rng_4bits

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.25 %
  • code
  • 87.87 %
  • assert
  • 83.42 %
  • func
  • 51.47 %
  • block
  • 94.43 %
  • line
  • 97.09 %
  • branch
  • 86.58 %
  • toggle
  • 76.12 %
  • FSM
  • 91.67 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 188.979us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 3.000s 43.235us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 204.706us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 4.000s 572.022us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 123.081us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 102.919us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 204.706us 1 1 100.00
entropy_src_csr_aliasing 3.000s 123.081us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 188.979us 1 1 100.00
entropy_src_rng 176.000s 13021.893us 1 1 100.00
entropy_src_fw_ov 52.000s 13212.532us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 52.000s 13212.532us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 176.000s 13021.893us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 100.000s 14041.187us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 176.000s 13021.893us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 176.000s 13021.893us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 176.000s 13021.893us 1 1 100.00
entropy_src_intr 8.000s 2427.614us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 176.000s 13021.893us 1 1 100.00
entropy_src_functional_alerts 4.000s 696.525us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 123.000s 14697.414us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 172.453us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 2.000s 80.919us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 1.000s 73.254us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 1.000s 88.551us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 3.000s 223.991us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 3.000s 223.991us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 3.000s 43.235us 1 1 100.00
entropy_src_csr_rw 2.000s 204.706us 1 1 100.00
entropy_src_csr_aliasing 3.000s 123.081us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 48.028us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 3.000s 43.235us 1 1 100.00
entropy_src_csr_rw 2.000s 204.706us 1 1 100.00
entropy_src_csr_aliasing 3.000s 123.081us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 48.028us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 99.116us 1 1 100.00
entropy_src_tl_intg_err 3.000s 187.828us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 176.000s 13021.893us 1 1 100.00
entropy_src_cfg_regwen 1.000s 19.041us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 176.000s 13021.893us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 176.000s 13021.893us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 176.000s 13021.893us 1 1 100.00
entropy_src_fw_ov 52.000s 13212.532us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 172.453us 1 1 100.00
entropy_src_sec_cm 2.000s 99.116us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 172.453us 1 1 100.00
entropy_src_sec_cm 2.000s 99.116us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 176.000s 13021.893us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 172.453us 1 1 100.00
entropy_src_sec_cm 2.000s 99.116us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 172.453us 1 1 100.00
entropy_src_sec_cm 2.000s 99.116us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 172.453us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 4.000s 696.525us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 187.828us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 199.000s 14035.934us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 10.000s 1939.309us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_lo_threshold 1 test run
entropy_src_stress_all_with_rand_reset 45905574948150819499625732662524246540004203548542241803093051566415295432817 124
UVM_INFO @ 1939309169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_lo_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 54804647412789324530006758397439167251927796840712037202188026754207793021560 113
UVM_INFO @ 102918639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---