Simulation Results: flash_ctrl

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.64 %
  • code
  • 94.06 %
  • assert
  • 96.94 %
  • func
  • 95.91 %
  • line
  • 95.91 %
  • branch
  • 96.99 %
  • cond
  • 93.81 %
  • toggle
  • 97.89 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
98.28%
V2S
91.67%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 56.020s 363.801us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 13.380s 35.871us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 15.360s 148.912us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 12.640s 91.711us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 24.130s 499.621us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 31.380s 1770.288us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 10.390s 110.460us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 12.640s 91.711us 1 1 100.00
flash_ctrl_csr_aliasing 31.380s 1770.288us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.850s 53.008us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.680s 62.363us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 13.050s 43.447us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 15.870s 54.018us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1157.630s 398328.268us 1 1 100.00
flash_ctrl_hw_rma_reset 623.190s 160195.800us 1 1 100.00
flash_ctrl_lcmgr_intg 7.420s 83.189us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1109.060s 275924.879us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 170.150s 5265.390us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 8.320s 84.576us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2065.480s 110537.624us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 76.380s 20778.942us 1 1 100.00
rd_buff_eviction_w_ecc 2 3 66.67
flash_ctrl_rw_evict 13.620s 57.855us 0 1 0.00
flash_ctrl_rw_evict_all_en 18.320s 96.231us 1 1 100.00
flash_ctrl_re_evict 20.740s 155.652us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 47.770s 45.345us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 47.770s 45.345us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 208.270s 20996.459us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 12.940s 365.618us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 353.850s 168.876us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 511.590s 11615.547us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 297.780s 1534.106us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 1181.470s 2428.584us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.800s 40.233us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 141.530s 6445.971us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.040s 40.732us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 5.720s 52.678us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 538.020s 1264.218us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 27.910s 1360.064us 1 1 100.00
flash_ctrl_otp_reset 60.460s 141.052us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1157.630s 398328.268us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 96.860s 1137.762us 1 1 100.00
flash_ctrl_intr_wr 45.980s 2755.624us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 180.210s 42828.772us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 139.410s 25448.101us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 45.950s 1867.302us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 35.220s 884.361us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 11.070s 78.503us 1 1 100.00
flash_ctrl_ro_derr 88.650s 2441.882us 1 1 100.00
flash_ctrl_rw_derr 122.330s 1233.456us 1 1 100.00
flash_ctrl_derr_detect 103.240s 7631.706us 1 1 100.00
flash_ctrl_integrity 418.840s 16587.848us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 11.950s 110.972us 1 1 100.00
flash_ctrl_ro_serr 96.860s 802.534us 1 1 100.00
flash_ctrl_rw_serr 144.930s 7801.759us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 55.090s 1040.357us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 36.360s 714.713us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 106.140s 2934.059us 1 1 100.00
flash_ctrl_write_word_sweep 7.450s 157.362us 1 1 100.00
flash_ctrl_read_word_sweep 6.580s 103.998us 1 1 100.00
flash_ctrl_ro 86.910s 1349.052us 1 1 100.00
flash_ctrl_rw 356.680s 4438.612us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 24.290s 358.940us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 537.990s 39837.820us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 55.350s 10020.232us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.390s 117.507us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.130s 56.337us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 16.440s 145.089us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 16.440s 145.089us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 15.360s 148.912us 1 1 100.00
flash_ctrl_csr_rw 12.640s 91.711us 1 1 100.00
flash_ctrl_csr_aliasing 31.380s 1770.288us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.150s 438.321us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 15.360s 148.912us 1 1 100.00
flash_ctrl_csr_rw 12.640s 91.711us 1 1 100.00
flash_ctrl_csr_aliasing 31.380s 1770.288us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.150s 438.321us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 25.610s 86.964us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 25.610s 86.964us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 25.610s 86.964us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 25.610s 86.964us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 17.060s 709.128us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1650.120s 1779.314us 1 1 100.00
flash_ctrl_tl_intg_err 397.980s 1394.459us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 397.980s 1394.459us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 397.980s 1394.459us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 16.550s 73.079us 1 1 100.00
flash_ctrl_wr_intg 6.960s 61.418us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 56.020s 363.801us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 60.460s 141.052us 1 1 100.00
flash_ctrl_disable 10.040s 40.732us 1 1 100.00
flash_ctrl_sec_info_access 46.570s 4704.445us 1 1 100.00
flash_ctrl_connect 5.720s 52.678us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 7.580s 21.983us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 12.640s 91.711us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 25.610s 86.964us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 12.640s 91.711us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 25.610s 86.964us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 12.640s 91.711us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 25.610s 86.964us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.040s 40.732us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 16.550s 73.079us 1 1 100.00
flash_ctrl_access_after_disable 6.330s 40.840us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 14.370s 76.688us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.040s 40.732us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 12.940s 365.618us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 356.680s 4438.612us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 144.930s 7801.759us 1 1 100.00
flash_ctrl_rw_derr 122.330s 1233.456us 1 1 100.00
flash_ctrl_integrity 418.840s 16587.848us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1157.630s 398328.268us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1650.120s 1779.314us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1650.120s 1779.314us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1650.120s 1779.314us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1650.120s 1779.314us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 8.090s 854.607us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 0 1 0.00
flash_ctrl_phy_host_grant_err 7.430s 7.746us 0 1 0.00
sec_cm_phy_ack_ctrl_consistency 0 1 0.00
flash_ctrl_phy_ack_consistency 11.740s 45.328us 0 1 0.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1650.120s 1779.314us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1650.120s 1779.314us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1650.120s 1779.314us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 23.000s 207.276us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 296.090s 3100.645us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * 1 test run
flash_ctrl_rw_evict 14311552418089666537191255152669958001604356650681475176341630684109670013368 108
UVM_INFO @ 57854.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' 1 test run
flash_ctrl_phy_host_grant_err 38776235675391829471321956920147820760632842556557526676656562461484330449942 125
UVM_ERROR @ 7746.0 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 7746.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) 1 test run
flash_ctrl_phy_ack_consistency 87633173089742574102105391287691043865092859518545168359021908153427854798340 109
UVM_INFO @ 45328.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---