Simulation Results: hmac

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.05 %
  • code
  • 98.27 %
  • assert
  • 97.38 %
  • func
  • 44.50 %
  • line
  • 99.64 %
  • branch
  • 98.84 %
  • cond
  • 95.79 %
  • toggle
  • 100.00 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 11.940s 2001.681us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.810s 113.698us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.920s 16.382us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 5.030s 648.315us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.970s 508.135us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.130s 44.371us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.920s 16.382us 1 1 100.00
hmac_csr_aliasing 6.970s 508.135us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 20.290s 19245.097us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 21.990s 2353.559us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.580s 848.023us 1 1 100.00
hmac_test_sha384_vectors 22.680s 319.300us 1 1 100.00
hmac_test_sha512_vectors 394.440s 16958.012us 1 1 100.00
hmac_test_hmac256_vectors 12.180s 1720.185us 1 1 100.00
hmac_test_hmac384_vectors 9.580s 347.455us 1 1 100.00
hmac_test_hmac512_vectors 9.930s 1464.185us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 3.200s 331.990us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 1122.880s 22917.166us 1 1 100.00
error 1 1 100.00
hmac_error 115.420s 6831.958us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 52.800s 1803.389us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 11.940s 2001.681us 1 1 100.00
hmac_long_msg 20.290s 19245.097us 1 1 100.00
hmac_back_pressure 21.990s 2353.559us 1 1 100.00
hmac_datapath_stress 1122.880s 22917.166us 1 1 100.00
hmac_burst_wr 3.200s 331.990us 1 1 100.00
hmac_stress_all 191.770s 26851.131us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 11.940s 2001.681us 1 1 100.00
hmac_long_msg 20.290s 19245.097us 1 1 100.00
hmac_back_pressure 21.990s 2353.559us 1 1 100.00
hmac_datapath_stress 1122.880s 22917.166us 1 1 100.00
hmac_wipe_secret 52.800s 1803.389us 1 1 100.00
hmac_test_sha256_vectors 8.580s 848.023us 1 1 100.00
hmac_test_sha384_vectors 22.680s 319.300us 1 1 100.00
hmac_test_sha512_vectors 394.440s 16958.012us 1 1 100.00
hmac_test_hmac256_vectors 12.180s 1720.185us 1 1 100.00
hmac_test_hmac384_vectors 9.580s 347.455us 1 1 100.00
hmac_test_hmac512_vectors 9.930s 1464.185us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 11.940s 2001.681us 1 1 100.00
hmac_long_msg 20.290s 19245.097us 1 1 100.00
hmac_back_pressure 21.990s 2353.559us 1 1 100.00
hmac_datapath_stress 1122.880s 22917.166us 1 1 100.00
hmac_burst_wr 3.200s 331.990us 1 1 100.00
hmac_error 115.420s 6831.958us 1 1 100.00
hmac_wipe_secret 52.800s 1803.389us 1 1 100.00
hmac_test_sha256_vectors 8.580s 848.023us 1 1 100.00
hmac_test_sha384_vectors 22.680s 319.300us 1 1 100.00
hmac_test_sha512_vectors 394.440s 16958.012us 1 1 100.00
hmac_test_hmac256_vectors 12.180s 1720.185us 1 1 100.00
hmac_test_hmac384_vectors 9.580s 347.455us 1 1 100.00
hmac_test_hmac512_vectors 9.930s 1464.185us 1 1 100.00
hmac_stress_all 191.770s 26851.131us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 191.770s 26851.131us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.740s 50.008us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.710s 46.917us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.640s 63.568us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.640s 63.568us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.810s 113.698us 1 1 100.00
hmac_csr_rw 0.920s 16.382us 1 1 100.00
hmac_csr_aliasing 6.970s 508.135us 1 1 100.00
hmac_same_csr_outstanding 2.220s 1465.287us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.810s 113.698us 1 1 100.00
hmac_csr_rw 0.920s 16.382us 1 1 100.00
hmac_csr_aliasing 6.970s 508.135us 1 1 100.00
hmac_same_csr_outstanding 2.220s 1465.287us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.010s 63.334us 1 1 100.00
hmac_tl_intg_err 2.200s 330.403us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.200s 330.403us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 11.940s 2001.681us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.820s 93.394us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 65.110s 4947.766us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.930s 36.540us 1 1 100.00