Simulation Results: i2c

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.93 %
  • code
  • 81.78 %
  • assert
  • 97.46 %
  • func
  • 78.54 %
  • line
  • 96.41 %
  • branch
  • 92.33 %
  • cond
  • 85.46 %
  • toggle
  • 89.45 %
  • FSM
  • 45.24 %
Validation stages
V1
100.00%
V2
90.24%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 11.830s 1341.509us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 6.280s 1411.572us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.890s 22.546us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.990s 50.554us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 4.710s 582.280us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.740s 43.252us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.870s 94.071us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.990s 50.554us 1 1 100.00
i2c_csr_aliasing 1.740s 43.252us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 1 1 100.00
i2c_host_error_intr 1.370s 57.739us 1 1 100.00
host_stress_all 0 1 0.00
i2c_host_stress_all 1933.330s 127540.165us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 44.080s 12442.213us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.980s 19.138us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 90.760s 2830.423us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 77.740s 2116.649us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.360s 486.734us 1 1 100.00
i2c_host_fifo_fmt_empty 4.820s 652.551us 1 1 100.00
i2c_host_fifo_reset_rx 6.810s 225.946us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 85.520s 10682.534us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 10.420s 4191.412us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 1.620s 260.903us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 1.610s 1425.523us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 37.500s 38494.793us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 2.180s 794.933us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 7.330s 530.799us 1 1 100.00
i2c_target_intr_smoke 3.850s 928.416us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.610s 290.571us 1 1 100.00
i2c_target_fifo_reset_tx 1.270s 509.042us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 16.760s 14266.838us 1 1 100.00
i2c_target_stress_rd 7.330s 530.799us 1 1 100.00
i2c_target_intr_stress_wr 254.140s 24354.981us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 5.570s 9394.596us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 2.040s 5297.918us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 3.260s 743.305us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 4.620s 10328.134us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 2.190s 1848.944us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.330s 179.932us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 44.080s 12442.213us 1 1 100.00
i2c_host_perf_precise 7.490s 768.722us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 10.420s 4191.412us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 2.700s 166.785us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 2.730s 578.742us 1 1 100.00
i2c_target_nack_acqfull_addr 1.720s 512.234us 1 1 100.00
i2c_target_nack_txstretch 1.120s 571.816us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 10.800s 1713.499us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.510s 627.913us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.800s 17.209us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.770s 130.950us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 2.150s 196.112us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 2.150s 196.112us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.890s 22.546us 1 1 100.00
i2c_csr_rw 0.990s 50.554us 1 1 100.00
i2c_csr_aliasing 1.740s 43.252us 1 1 100.00
i2c_same_csr_outstanding 1.060s 41.337us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.890s 22.546us 1 1 100.00
i2c_csr_rw 0.990s 50.554us 1 1 100.00
i2c_csr_aliasing 1.740s 43.252us 1 1 100.00
i2c_same_csr_outstanding 1.060s 41.337us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.860s 146.489us 1 1 100.00
i2c_sec_cm 0.990s 150.541us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.860s 146.489us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 6.100s 875.863us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 0.920s 119.452us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 21.420s 1952.089us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: 2 test runs
i2c_host_stress_all 33489723131629026779475231307223705556885087226946748442186214096086072882908 143
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @12383072
i2c_host_mode_toggle 12223306823374383124697221837682433805368320798729299556026981007295481822476 85
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @21837
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
i2c_host_stress_all_with_rand_reset 48127426561690648220744834256875789276146240402978507769700740768684165385097 94
UVM_INFO @ 875863121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 90800806516765298382315639083897667593734676707907481188870346242982004217160 95
UVM_INFO @ 1952089116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 82233440958049802879833657894356869034518218071302240028777159908915645874414 84
UVM_INFO @ 1425523318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 70133259081456596325361552360175489362781504496392412636223848926781526421954 78
UVM_INFO @ 119451726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! 1 test run
i2c_target_hrst 78700387384724394096110064137361630750234529547315198360069460856748394159722 79
UVM_INFO @ 10328133639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---