Simulation Results: kmac/masked

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.13 %
  • code
  • 67.16 %
  • assert
  • 96.48 %
  • func
  • 76.76 %
  • line
  • 95.19 %
  • branch
  • 88.95 %
  • cond
  • 83.93 %
  • toggle
  • 29.14 %
  • FSM
  • 38.61 %
Validation stages
V1
100.00%
V2
62.07%
V2S
75.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 38.860s 1507.392us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.850s 28.299us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.900s 87.518us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 9.200s 3725.240us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 7.940s 8012.404us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.350s 30.338us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.900s 87.518us 1 1 100.00
kmac_csr_aliasing 7.940s 8012.404us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.860s 13.626us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.230s 117.705us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 890.770s 168814.341us 1 1 100.00
burst_write 0 1 0.00
kmac_burst_write 862.330s 500000.000us 0 1 0.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1763.460s 333006.954us 1 1 100.00
kmac_test_vectors_sha3_256 31.210s 6058.690us 1 1 100.00
kmac_test_vectors_sha3_384 21.780s 3703.316us 1 1 100.00
kmac_test_vectors_sha3_512 1123.260s 193505.686us 1 1 100.00
kmac_test_vectors_shake_128 200.540s 20880.136us 1 1 100.00
kmac_test_vectors_shake_256 113.020s 30433.561us 1 1 100.00
kmac_test_vectors_kmac 3.000s 782.060us 1 1 100.00
kmac_test_vectors_kmac_xof 1.960s 55.538us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 285.640s 77607.775us 1 1 100.00
app 0 1 0.00
kmac_app 3.260s 99.521us 0 1 0.00
app_with_partial_data 0 1 0.00
kmac_app_with_partial_data 1.760s 287.767us 0 1 0.00
entropy_refresh 0 1 0.00
kmac_entropy_refresh 9.260s 549.399us 0 1 0.00
error 0 1 0.00
kmac_error 22.470s 2252.282us 0 1 0.00
key_error 0 1 0.00
kmac_key_error 1.190s 80.560us 0 1 0.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 1.000s 12.510us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 12.080s 817.247us 1 1 100.00
entropy_mode_error 0 1 0.00
kmac_entropy_mode_error 26.360s 2221.868us 0 1 0.00
entropy_ready_error 0 1 0.00
kmac_entropy_ready_error 1.270s 40.172us 0 1 0.00
lc_escalation 0 1 0.00
kmac_lc_escalation 1.060s 17.089us 0 1 0.00
stress_all 0 1 0.00
kmac_stress_all 35.350s 20553.863us 0 1 0.00
intr_test 1 1 100.00
kmac_intr_test 0.940s 11.940us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.100s 52.424us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.210s 58.447us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.210s 58.447us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.850s 28.299us 1 1 100.00
kmac_csr_rw 0.900s 87.518us 1 1 100.00
kmac_csr_aliasing 7.940s 8012.404us 1 1 100.00
kmac_same_csr_outstanding 1.840s 48.843us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.850s 28.299us 1 1 100.00
kmac_csr_rw 0.900s 87.518us 1 1 100.00
kmac_csr_aliasing 7.940s 8012.404us 1 1 100.00
kmac_same_csr_outstanding 1.840s 48.843us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.750s 134.700us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.750s 134.700us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.750s 134.700us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.750s 134.700us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.600s 265.191us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 87.820s 43211.511us 1 1 100.00
kmac_tl_intg_err 2.490s 535.109us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.490s 535.109us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
kmac_lc_escalation 1.060s 17.089us 0 1 0.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 38.860s 1507.392us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 285.640s 77607.775us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.750s 134.700us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 87.820s 43211.511us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 87.820s 43211.511us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 87.820s 43211.511us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 38.860s 1507.392us 1 1 100.00
sec_cm_fsm_global_esc 0 1 0.00
kmac_lc_escalation 1.060s 17.089us 0 1 0.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 87.820s 43211.511us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 0 1 0.00
kmac_mubi 28.130s 642.576us 0 1 0.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 38.860s 1507.392us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 2.800s 359.071us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] 7 test runs
kmac_app 10525943638226098360096023048836956295435704222502210620509388046714665774928 78
UVM_INFO @ 99520542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app_with_partial_data 95035028970949356860450961029299824461250378442765049931897452741407816061226 78
UVM_INFO @ 287767202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_refresh 55424077230561455861527748665186109877267108860080103607343310666507937859681 81
UVM_INFO @ 549398674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_error 76372792434690255813831098050890481177425533281293327690499949844351204083664 90
UVM_INFO @ 2252282310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_ready_error 109441812109720532013309433296864669296547771148068183811907117878585666455398 77
UVM_INFO @ 40171691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_lc_escalation 43882051323691376213665302823081757922407663044867393118660842351079267470128 80
UVM_INFO @ 17088752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 109523488015317701869905772312770954868095429320350219412080778340044862733508 94
UVM_INFO @ 359070930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))' 3 test runs
kmac_sideload_invalid 76095862434118651480132143467962484810379040936507428429316485547321045599942 79
UVM_ERROR @ 12510011 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 12510011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_key_error 11119269552924903440794607686002252418191483970017763277414241852201889992111 78
UVM_ERROR @ 80560248 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 80560248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_mode_error 67257694466186147623166090314888017397510025608962562396991189862634106829809 91
UVM_ERROR @ 2221868203 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 2221868203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err) 2 test runs
kmac_mubi 91799959625126152877117005179018960491054723157789954486662551831870358212974 92
UVM_INFO @ 642576335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 45783276193952800273209158369402193745223667839520913034229410646993573008956 176
UVM_INFO @ 20553863462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
kmac_burst_write 22568635189964551704060154704211071239209108128561685577199356439156159256359 198
UVM_INFO @ 500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---