Simulation Results: kmac/unmasked

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.57 %
  • code
  • 65.40 %
  • assert
  • 96.35 %
  • func
  • 73.96 %
  • line
  • 92.87 %
  • branch
  • 87.28 %
  • cond
  • 82.99 %
  • toggle
  • 27.34 %
  • FSM
  • 36.50 %
Validation stages
V1
100.00%
V2
68.97%
V2S
75.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 40.760s 1320.648us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.200s 28.226us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.010s 36.011us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 12.130s 422.044us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 7.550s 516.281us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.420s 87.222us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.010s 36.011us 1 1 100.00
kmac_csr_aliasing 7.550s 516.281us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.740s 29.256us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.390s 40.144us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 1041.540s 213263.908us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 210.360s 39460.951us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 30.630s 2885.312us 1 1 100.00
kmac_test_vectors_sha3_256 1314.420s 106464.932us 1 1 100.00
kmac_test_vectors_sha3_384 1453.420s 334265.218us 1 1 100.00
kmac_test_vectors_sha3_512 14.500s 1395.764us 1 1 100.00
kmac_test_vectors_shake_128 150.430s 31773.713us 1 1 100.00
kmac_test_vectors_shake_256 2278.020s 456626.913us 1 1 100.00
kmac_test_vectors_kmac 1.970s 183.295us 1 1 100.00
kmac_test_vectors_kmac_xof 2.310s 541.109us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 192.520s 18762.161us 1 1 100.00
app 0 1 0.00
kmac_app 2.900s 392.638us 0 1 0.00
app_with_partial_data 0 1 0.00
kmac_app_with_partial_data 3.070s 933.836us 0 1 0.00
entropy_refresh 0 1 0.00
kmac_entropy_refresh 2.780s 909.901us 0 1 0.00
error 0 1 0.00
kmac_error 66.990s 4374.323us 0 1 0.00
key_error 0 1 0.00
kmac_key_error 0.970s 7.731us 0 1 0.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 0.870s 3.386us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 4.660s 398.719us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 5.410s 263.353us 1 1 100.00
entropy_ready_error 0 1 0.00
kmac_entropy_ready_error 1.290s 280.804us 0 1 0.00
lc_escalation 0 1 0.00
kmac_lc_escalation 1.300s 98.553us 0 1 0.00
stress_all 0 1 0.00
kmac_stress_all 114.040s 12805.346us 0 1 0.00
intr_test 1 1 100.00
kmac_intr_test 0.700s 59.862us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.830s 17.358us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.880s 80.884us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.880s 80.884us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.200s 28.226us 1 1 100.00
kmac_csr_rw 1.010s 36.011us 1 1 100.00
kmac_csr_aliasing 7.550s 516.281us 1 1 100.00
kmac_same_csr_outstanding 1.560s 252.875us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.200s 28.226us 1 1 100.00
kmac_csr_rw 1.010s 36.011us 1 1 100.00
kmac_csr_aliasing 7.550s 516.281us 1 1 100.00
kmac_same_csr_outstanding 1.560s 252.875us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.200s 42.523us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.200s 42.523us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.200s 42.523us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.200s 42.523us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 1.690s 47.899us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 29.490s 3421.081us 1 1 100.00
kmac_tl_intg_err 4.570s 875.454us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 4.570s 875.454us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
kmac_lc_escalation 1.300s 98.553us 0 1 0.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 40.760s 1320.648us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 192.520s 18762.161us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.200s 42.523us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 29.490s 3421.081us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 29.490s 3421.081us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 29.490s 3421.081us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 40.760s 1320.648us 1 1 100.00
sec_cm_fsm_global_esc 0 1 0.00
kmac_lc_escalation 1.300s 98.553us 0 1 0.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 29.490s 3421.081us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 0 1 0.00
kmac_mubi 0.940s 220.327us 0 1 0.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 40.760s 1320.648us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 65.100s 7164.015us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] 5 test runs
kmac_app 72809801687044200782982844883775932599012006060937908714155309485259576448400 78
UVM_INFO @ 392638019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app_with_partial_data 39584483487145320018416410160509152088289104887193698045833127165268808862551 79
UVM_INFO @ 933835501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_refresh 53682782193318582367756715889029954062590789117559781835229754608173842441411 78
UVM_INFO @ 909901274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_error 108881665051934725091792690693532967087374756130284857305939651413786794529144 117
UVM_INFO @ 4374322701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_ready_error 39675294625999910905690107597690870967293151180195181496132220487956554985071 77
UVM_INFO @ 280804438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))' 2 test runs
kmac_sideload_invalid 22504244057355438041948399338924553519302183626602602033793693972657186267107 79
UVM_ERROR @ 3385901 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 3385901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_key_error 81838939831906947751195589857207698579154929475170868473252531511617555430889 78
UVM_ERROR @ 7730782 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 7730782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err) 2 test runs
kmac_mubi 61131341782463434096560127051764050194257561433302386715616562720235272478258 77
UVM_INFO @ 220326645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 92595972695816144995542168787988290307742311485093379127126812573383720916869 124
UVM_INFO @ 12805345812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!kmac_data_req.req_valid)' 1 test run
kmac_lc_escalation 81771527640276764896645173446110549913220106315296119432680032646958237665512 78
UVM_ERROR @ 98553286 ps: (kmac_app_intf.sv:77) [ASSERT FAILED] DoneAssertAfterLast_A
UVM_INFO @ 98553286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
kmac_stress_all_with_rand_reset 32608887019609186250577608249593115983293503356825563796854147079001848610537 207
UVM_INFO @ 7164015103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---