Simulation Results: lc_ctrl/volatile_unlock_disabled

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.24 %
  • code
  • 83.71 %
  • assert
  • 94.13 %
  • func
  • 92.88 %
  • line
  • 97.15 %
  • branch
  • 93.70 %
  • cond
  • 79.22 %
  • toggle
  • 85.88 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.040s 855.201us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.930s 22.325us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.920s 18.640us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.220s 23.859us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 99.396us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.070s 30.090us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.920s 18.640us 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 99.396us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.560s 622.859us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 13.870s 1836.481us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.930s 12.637us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.700s 302.720us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.260s 2471.660us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.510s 1404.732us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.260s 2471.660us 1 1 100.00
lc_ctrl_prog_failure 2.700s 302.720us 1 1 100.00
lc_ctrl_errors 6.510s 1404.732us 1 1 100.00
lc_ctrl_security_escalation 7.260s 450.609us 1 1 100.00
lc_ctrl_jtag_state_failure 15.980s 1172.165us 1 1 100.00
lc_ctrl_jtag_prog_failure 17.820s 7404.502us 1 1 100.00
lc_ctrl_jtag_errors 43.230s 2327.916us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.720s 106.819us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.680s 1484.571us 1 1 100.00
lc_ctrl_jtag_prog_failure 17.820s 7404.502us 1 1 100.00
lc_ctrl_jtag_errors 43.230s 2327.916us 1 1 100.00
lc_ctrl_jtag_access 4.390s 4506.619us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.900s 2735.241us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.800s 588.528us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.630s 367.409us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.460s 475.415us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.050s 401.843us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.080s 50.253us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.220s 890.115us 1 1 100.00
lc_ctrl_jtag_alert_test 1.110s 89.658us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.730s 428.042us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.940s 15.267us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 88.320s 39934.524us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.030s 39.638us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.180s 1105.404us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.180s 1105.404us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.930s 22.325us 1 1 100.00
lc_ctrl_csr_rw 0.920s 18.640us 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 99.396us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.210s 289.426us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.930s 22.325us 1 1 100.00
lc_ctrl_csr_rw 0.920s 18.640us 1 1 100.00
lc_ctrl_csr_aliasing 1.220s 99.396us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.210s 289.426us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.640s 1238.600us 1 1 100.00
lc_ctrl_tl_intg_err 1.920s 67.567us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.920s 67.567us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 13.870s 1836.481us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.260s 2471.660us 1 1 100.00
lc_ctrl_sec_cm 7.640s 1238.600us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.260s 2471.660us 1 1 100.00
lc_ctrl_sec_cm 7.640s 1238.600us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.260s 2471.660us 1 1 100.00
lc_ctrl_sec_cm 7.640s 1238.600us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.260s 2471.660us 1 1 100.00
lc_ctrl_sec_cm 7.640s 1238.600us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.260s 2471.660us 1 1 100.00
lc_ctrl_sec_cm 7.640s 1238.600us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.260s 2471.660us 1 1 100.00
lc_ctrl_sec_cm 7.640s 1238.600us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.260s 2471.660us 1 1 100.00
lc_ctrl_sec_cm 7.640s 1238.600us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.260s 2471.660us 1 1 100.00
lc_ctrl_sec_cm 7.640s 1238.600us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.260s 450.609us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.560s 622.859us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.680s 1484.571us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.170s 4144.224us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.170s 4144.224us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.460s 815.084us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.300s 1464.786us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.300s 1464.786us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3.940s 237.937us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 4512195599711199618835033367061353658036025017388588550472726711231944121809 155
UVM_INFO @ 237936634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---