Simulation Results: lc_ctrl/volatile_unlock_enabled

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.53 %
  • code
  • 84.13 %
  • assert
  • 95.11 %
  • func
  • 92.35 %
  • line
  • 97.22 %
  • branch
  • 93.66 %
  • cond
  • 79.54 %
  • toggle
  • 86.66 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.330s 54.373us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.930s 46.437us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.100s 13.622us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.270s 145.243us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.920s 17.347us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.420s 54.559us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.100s 13.622us 1 1 100.00
lc_ctrl_csr_aliasing 0.920s 17.347us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.200s 251.899us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.910s 414.696us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.790s 13.557us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.820s 123.369us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.530s 532.234us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 3.470s 2188.948us 1 1 100.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 6.530s 532.234us 1 1 100.00
lc_ctrl_prog_failure 1.820s 123.369us 1 1 100.00
lc_ctrl_errors 3.470s 2188.948us 1 1 100.00
lc_ctrl_security_escalation 8.430s 319.007us 1 1 100.00
lc_ctrl_jtag_state_failure 19.910s 18290.495us 1 1 100.00
lc_ctrl_jtag_prog_failure 11.800s 639.558us 1 1 100.00
lc_ctrl_jtag_errors 3.410s 249.516us 0 1 0.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 2.810s 1005.895us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.580s 1023.374us 1 1 100.00
lc_ctrl_jtag_prog_failure 11.800s 639.558us 1 1 100.00
lc_ctrl_jtag_errors 3.410s 249.516us 0 1 0.00
lc_ctrl_jtag_access 1.880s 197.858us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.150s 1070.039us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.100s 144.314us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.690s 35.060us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.950s 2328.893us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 18.270s 1117.388us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.330s 98.223us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.210s 142.152us 1 1 100.00
lc_ctrl_jtag_alert_test 0.790s 282.195us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 8.750s 450.450us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.900s 24.860us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 32.480s 13548.936us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.150s 66.665us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.350s 23.141us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.350s 23.141us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.930s 46.437us 1 1 100.00
lc_ctrl_csr_rw 1.100s 13.622us 1 1 100.00
lc_ctrl_csr_aliasing 0.920s 17.347us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.210s 46.787us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.930s 46.437us 1 1 100.00
lc_ctrl_csr_rw 1.100s 13.622us 1 1 100.00
lc_ctrl_csr_aliasing 0.920s 17.347us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.210s 46.787us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.210s 230.034us 1 1 100.00
lc_ctrl_tl_intg_err 1.720s 68.826us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.720s 68.826us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.910s 414.696us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.530s 532.234us 1 1 100.00
lc_ctrl_sec_cm 7.210s 230.034us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.530s 532.234us 1 1 100.00
lc_ctrl_sec_cm 7.210s 230.034us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.530s 532.234us 1 1 100.00
lc_ctrl_sec_cm 7.210s 230.034us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.530s 532.234us 1 1 100.00
lc_ctrl_sec_cm 7.210s 230.034us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.530s 532.234us 1 1 100.00
lc_ctrl_sec_cm 7.210s 230.034us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.530s 532.234us 1 1 100.00
lc_ctrl_sec_cm 7.210s 230.034us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.530s 532.234us 1 1 100.00
lc_ctrl_sec_cm 7.210s 230.034us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.530s 532.234us 1 1 100.00
lc_ctrl_sec_cm 7.210s 230.034us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 8.430s 319.007us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.200s 251.899us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.580s 1023.374us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.920s 925.014us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.920s 925.014us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.600s 411.349us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.240s 2901.526us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.240s 2901.526us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 40.180s 18623.031us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_jtag_errors 54283661091682650929461379555386571869191022061672330321355031769621294343057 243
UVM_INFO @ 249516442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---