| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
88.00% |
| V3 |
|
0.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| otbn_smoke | 9.000s | 142.572us | 1 | 1 | 100.00 | |
| single_binary | 1 | 1 | 100.00 | |||
| otbn_single | 13.000s | 57.908us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| otbn_csr_hw_reset | 27.000s | 14.127us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| otbn_csr_rw | 28.000s | 20.889us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| otbn_csr_bit_bash | 28.000s | 32.210us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| otbn_csr_aliasing | 28.000s | 24.172us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| otbn_csr_mem_rw_with_rand_reset | 30.000s | 141.866us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| otbn_csr_rw | 28.000s | 20.889us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 28.000s | 24.172us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| otbn_mem_walk | 46.000s | 2913.664us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| otbn_mem_partial_access | 27.000s | 4594.516us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reset_recovery | 1 | 1 | 100.00 | |||
| otbn_reset | 21.000s | 69.859us | 1 | 1 | 100.00 | |
| multi_error | 1 | 1 | 100.00 | |||
| otbn_multi_err | 60.000s | 310.233us | 1 | 1 | 100.00 | |
| back_to_back | 1 | 1 | 100.00 | |||
| otbn_multi | 111.000s | 381.870us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| otbn_stress_all | 47.000s | 139.973us | 1 | 1 | 100.00 | |
| lc_escalation | 1 | 1 | 100.00 | |||
| otbn_escalate | 25.000s | 34.640us | 1 | 1 | 100.00 | |
| zero_state_err_urnd | 1 | 1 | 100.00 | |||
| otbn_zero_state_err_urnd | 6.000s | 123.291us | 1 | 1 | 100.00 | |
| sw_errs_fatal_chk | 1 | 1 | 100.00 | |||
| otbn_sw_errs_fatal_chk | 9.000s | 43.950us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| otbn_alert_test | 30.000s | 19.812us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| otbn_intr_test | 10.000s | 52.470us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 5.000s | 112.817us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 5.000s | 112.817us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 27.000s | 14.127us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 28.000s | 20.889us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 28.000s | 24.172us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 4.000s | 96.074us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 27.000s | 14.127us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 28.000s | 20.889us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 28.000s | 24.172us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 4.000s | 96.074us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mem_integrity | 2 | 2 | 100.00 | |||
| otbn_imem_err | 26.000s | 65.552us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 28.000s | 15.782us | 1 | 1 | 100.00 | |
| internal_integrity | 3 | 4 | 75.00 | |||
| otbn_alu_bignum_mod_err | 32.000s | 105.395us | 1 | 1 | 100.00 | |
| otbn_controller_ispr_rdata_err | 36.000s | 48.178us | 1 | 1 | 100.00 | |
| otbn_mac_bignum_acc_err | 0.812s | 0.000us | 0 | 1 | 0.00 | |
| otbn_urnd_err | 5.000s | 10.683us | 1 | 1 | 100.00 | |
| illegal_bus_access | 1 | 1 | 100.00 | |||
| otbn_illegal_mem_acc | 22.000s | 37.403us | 1 | 1 | 100.00 | |
| otbn_mem_gnt_acc_err | 1 | 1 | 100.00 | |||
| otbn_mem_gnt_acc_err | 8.000s | 37.847us | 1 | 1 | 100.00 | |
| otbn_non_sec_partial_wipe | 0 | 1 | 0.00 | |||
| otbn_partial_wipe | 4.000s | 16.041us | 0 | 1 | 0.00 | |
| tl_intg_err | 1 | 2 | 50.00 | |||
| otbn_sec_cm | 17.000s | 248.211us | 0 | 1 | 0.00 | |
| otbn_tl_intg_err | 17.000s | 478.150us | 1 | 1 | 100.00 | |
| passthru_mem_tl_intg_err | 1 | 1 | 100.00 | |||
| otbn_passthru_mem_tl_intg_err | 43.000s | 763.054us | 1 | 1 | 100.00 | |
| prim_fsm_check | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 17.000s | 248.211us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 17.000s | 248.211us | 0 | 1 | 0.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| otbn_smoke | 9.000s | 142.572us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_dmem_err | 28.000s | 15.782us | 1 | 1 | 100.00 | |
| sec_cm_instruction_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_imem_err | 26.000s | 65.552us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| otbn_tl_intg_err | 17.000s | 478.150us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_global_esc | 1 | 1 | 100.00 | |||
| otbn_escalate | 25.000s | 34.640us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_local_esc | 4 | 5 | 80.00 | |||
| otbn_imem_err | 26.000s | 65.552us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 28.000s | 15.782us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 6.000s | 123.291us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 22.000s | 37.403us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 17.000s | 248.211us | 0 | 1 | 0.00 | |
| sec_cm_controller_fsm_sparse | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 17.000s | 248.211us | 0 | 1 | 0.00 | |
| sec_cm_scramble_key_sideload | 1 | 1 | 100.00 | |||
| otbn_single | 13.000s | 57.908us | 1 | 1 | 100.00 | |
| sec_cm_scramble_ctrl_fsm_local_esc | 4 | 5 | 80.00 | |||
| otbn_imem_err | 26.000s | 65.552us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 28.000s | 15.782us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 6.000s | 123.291us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 22.000s | 37.403us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 17.000s | 248.211us | 0 | 1 | 0.00 | |
| sec_cm_scramble_ctrl_fsm_sparse | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 17.000s | 248.211us | 0 | 1 | 0.00 | |
| sec_cm_start_stop_ctrl_fsm_global_esc | 1 | 1 | 100.00 | |||
| otbn_escalate | 25.000s | 34.640us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_local_esc | 4 | 5 | 80.00 | |||
| otbn_imem_err | 26.000s | 65.552us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 28.000s | 15.782us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 6.000s | 123.291us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 22.000s | 37.403us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 17.000s | 248.211us | 0 | 1 | 0.00 | |
| sec_cm_start_stop_ctrl_fsm_sparse | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 17.000s | 248.211us | 0 | 1 | 0.00 | |
| sec_cm_data_reg_sw_sca | 1 | 1 | 100.00 | |||
| otbn_single | 13.000s | 57.908us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_redun | 1 | 1 | 100.00 | |||
| otbn_ctrl_redun | 29.000s | 36.376us | 1 | 1 | 100.00 | |
| sec_cm_pc_ctrl_flow_redun | 1 | 1 | 100.00 | |||
| otbn_pc_ctrl_flow_redun | 14.000s | 63.564us | 1 | 1 | 100.00 | |
| sec_cm_rnd_bus_consistency | 1 | 1 | 100.00 | |||
| otbn_rnd_sec_cm | 30.000s | 463.638us | 1 | 1 | 100.00 | |
| sec_cm_rnd_rng_digest | 1 | 1 | 100.00 | |||
| otbn_rnd_sec_cm | 30.000s | 463.638us | 1 | 1 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_integrity | 1 | 1 | 100.00 | |||
| otbn_rf_base_intg_err | 7.000s | 15.056us | 1 | 1 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_glitch_detect | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 17.000s | 248.211us | 0 | 1 | 0.00 | |
| sec_cm_stack_wr_ptr_ctr_redun | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 17.000s | 248.211us | 0 | 1 | 0.00 | |
| sec_cm_rf_bignum_data_reg_sw_integrity | 1 | 1 | 100.00 | |||
| otbn_rf_bignum_intg_err | 9.000s | 214.321us | 1 | 1 | 100.00 | |
| sec_cm_rf_bignum_data_reg_sw_glitch_detect | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 17.000s | 248.211us | 0 | 1 | 0.00 | |
| sec_cm_loop_stack_ctr_redun | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 17.000s | 248.211us | 0 | 1 | 0.00 | |
| sec_cm_loop_stack_addr_integrity | 1 | 1 | 100.00 | |||
| otbn_stack_addr_integ_chk | 16.000s | 64.642us | 1 | 1 | 100.00 | |
| sec_cm_call_stack_addr_integrity | 1 | 1 | 100.00 | |||
| otbn_stack_addr_integ_chk | 16.000s | 64.642us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_state_consistency | 1 | 1 | 100.00 | |||
| otbn_sec_wipe_err | 5.000s | 26.562us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 13.000s | 57.908us | 1 | 1 | 100.00 | |
| sec_cm_instruction_mem_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 13.000s | 57.908us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 13.000s | 57.908us | 1 | 1 | 100.00 | |
| sec_cm_write_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_multi | 111.000s | 381.870us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_flow_count | 1 | 1 | 100.00 | |||
| otbn_single | 13.000s | 57.908us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_flow_sca | 1 | 1 | 100.00 | |||
| otbn_single | 13.000s | 57.908us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_sw_noaccess | 1 | 1 | 100.00 | |||
| otbn_sw_no_acc | 6.000s | 78.805us | 1 | 1 | 100.00 | |
| sec_cm_key_sideload | 1 | 1 | 100.00 | |||
| otbn_single | 13.000s | 57.908us | 1 | 1 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 17.000s | 248.211us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| otbn_stress_all_with_rand_reset | 115.000s | 2341.124us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| otbn_smoke_vectorized | 7.000s | 145.556us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] | 1 test run | |||
| otbn_mac_bignum_acc_err | 2213650288804212358537978412484770777619303873663742563472992134702475284933 | None |
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
|
|
| UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) | 1 test run | |||
| otbn_stress_all_with_rand_reset | 16163421868497097907415415108743167710910396829364993129703608935757300554452 | 211 |
UVM_INFO @ 2341124116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,161): Assertion IdleIfLockedAndNotRotatingKeys_A has failed (* cycles, starting * PS) | 1 test run | |||
| otbn_partial_wipe | 85864375134137414226474405136544940023917821202492623426704929090867156212992 | 120 |
UVM_ERROR @ 16041287 ps: (otbn_idle_checker.sv:161) [ASSERT FAILED] IdleIfLockedAndNotRotatingKeys_A
UVM_INFO @ 16041287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed | 1 test run | |||
| otbn_sec_cm | 79706614282836348127477414162380558077637596717918367210952721387375010728476 | 127 |
UVM_ERROR @ 248210852 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 248210852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|