Simulation Results: otp_ctrl

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.95 %
  • code
  • 79.70 %
  • assert
  • 94.82 %
  • func
  • 77.34 %
  • line
  • 88.60 %
  • branch
  • 83.55 %
  • cond
  • 90.60 %
  • toggle
  • 90.46 %
  • FSM
  • 45.31 %
Validation stages
V1
100.00%
V2
95.00%
V2S
88.89%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.380s 207.207us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 4.130s 840.149us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.740s 1451.995us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.720s 79.872us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 9.890s 634.163us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.890s 363.735us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.030s 108.645us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.720s 79.872us 1 1 100.00
otp_ctrl_csr_aliasing 4.890s 363.735us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.860s 553.979us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.580s 37.546us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 14.940s 15017.592us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 5.970s 2260.779us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 10.240s 8714.150us 1 1 100.00
otp_ctrl_check_fail 4.810s 180.686us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 5.070s 354.438us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 10.050s 5557.942us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 7.150s 480.714us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 17.550s 8232.538us 1 1 100.00
otp_ctrl_parallel_lc_esc 2.290s 144.294us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 8.920s 507.771us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 16.200s 3847.929us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 16.970s 2602.152us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 168.530s 17761.514us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.390s 144.787us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.110s 97.082us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 2.620s 85.363us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 2.620s 85.363us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.740s 1451.995us 1 1 100.00
otp_ctrl_csr_rw 1.720s 79.872us 1 1 100.00
otp_ctrl_csr_aliasing 4.890s 363.735us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.030s 2136.138us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.740s 1451.995us 1 1 100.00
otp_ctrl_csr_rw 1.720s 79.872us 1 1 100.00
otp_ctrl_csr_aliasing 4.890s 363.735us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.030s 2136.138us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 102.570s 9470.125us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 102.570s 9470.125us 1 1 100.00
otp_ctrl_tl_intg_err 19.100s 19295.031us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 102.570s 9470.125us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 102.570s 9470.125us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 19.100s 19295.031us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 4.130s 840.149us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 4.130s 840.149us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 102.570s 9470.125us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 102.570s 9470.125us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 102.570s 9470.125us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 102.570s 9470.125us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 102.570s 9470.125us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 102.570s 9470.125us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 102.570s 9470.125us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 102.570s 9470.125us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 102.570s 9470.125us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 102.570s 9470.125us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 102.570s 9470.125us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 102.570s 9470.125us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 102.570s 9470.125us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 102.570s 9470.125us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 102.570s 9470.125us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.290s 144.294us 1 1 100.00
otp_ctrl_sec_cm 102.570s 9470.125us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.290s 144.294us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.290s 144.294us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.290s 144.294us 1 1 100.00
otp_ctrl_macro_errs 16.200s 3847.929us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.290s 144.294us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.290s 144.294us 1 1 100.00
otp_ctrl_sec_cm 102.570s 9470.125us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.290s 144.294us 1 1 100.00
otp_ctrl_sec_cm 102.570s 9470.125us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.290s 144.294us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.290s 144.294us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.290s 144.294us 1 1 100.00
otp_ctrl_macro_errs 16.200s 3847.929us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.290s 144.294us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.290s 144.294us 1 1 100.00
otp_ctrl_sec_cm 102.570s 9470.125us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 5.970s 2260.779us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 4.810s 180.686us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 10.050s 5557.942us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 10.050s 5557.942us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 10.050s 5557.942us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 10.050s 5557.942us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 10.050s 5557.942us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 4.130s 840.149us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 10.050s 5557.942us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 4.130s 840.149us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 102.570s 9470.125us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 5.070s 354.438us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 4.130s 840.149us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 4.130s 840.149us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 16.200s 3847.929us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 11.000s 8739.187us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 22.010s 4872.955us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_check_fail 72666272507202097360735579361284537534318127420108177091930594153601802378742 5570
UVM_INFO @ 180686388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_stress_all_with_rand_reset 24209661832943553820402536993145017888493567084227253519380995116428544660763 263
UVM_INFO @ 4872954701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---