Simulation Results: pwrmgr

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.21 %
  • code
  • 97.42 %
  • assert
  • 98.69 %
  • func
  • 98.52 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 96.04 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.620s 25.275us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.740s 30.646us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.840s 45.884us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.940s 260.673us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.960s 97.471us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.980s 120.587us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.840s 45.884us 1 1 100.00
pwrmgr_csr_aliasing 0.960s 97.471us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.920s 164.794us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.920s 164.794us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.810s 183.373us 1 1 100.00
pwrmgr_lowpower_invalid 0.730s 79.831us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.820s 64.979us 1 1 100.00
pwrmgr_reset_invalid 0.790s 122.046us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.820s 64.979us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.960s 539.813us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.730s 89.736us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.790s 179.492us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 4.440s 10723.418us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.700s 55.637us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.810s 84.294us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.810s 84.294us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.740s 30.646us 1 1 100.00
pwrmgr_csr_rw 0.840s 45.884us 1 1 100.00
pwrmgr_csr_aliasing 0.960s 97.471us 1 1 100.00
pwrmgr_same_csr_outstanding 0.840s 447.730us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.740s 30.646us 1 1 100.00
pwrmgr_csr_rw 0.840s 45.884us 1 1 100.00
pwrmgr_csr_aliasing 0.960s 97.471us 1 1 100.00
pwrmgr_same_csr_outstanding 0.840s 447.730us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 1.230s 434.466us 1 1 100.00
pwrmgr_sec_cm 1.250s 913.774us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.250s 913.774us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.250s 913.774us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 1.230s 434.466us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.980s 833.425us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.960s 539.813us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.860s 792.716us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.760s 71.949us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.630s 30.845us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.250s 913.774us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.250s 913.774us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.250s 913.774us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.570s 87.205us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.620s 42.756us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.810s 93.642us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.840s 45.884us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.840s 45.884us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.690s 408.886us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 7.350s 6331.334us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 1 test run
pwrmgr_stress_all 91311117461676422325545084068554168874157427916159216768844452472094972057489 592
UVM_INFO @ 10723418471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---