Simulation Results: rom_ctrl/32kb

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.65 %
  • code
  • 97.92 %
  • assert
  • 96.81 %
  • func
  • 95.23 %
  • line
  • 99.46 %
  • branch
  • 98.91 %
  • cond
  • 96.29 %
  • toggle
  • 94.96 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.580s 464.386us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.460s 129.959us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.580s 554.115us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.830s 537.943us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.820s 535.762us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.050s 182.729us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.580s 554.115us 1 1 100.00
rom_ctrl_csr_aliasing 4.820s 535.762us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.010s 371.687us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.780s 289.972us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.430s 83.537us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 14.850s 3381.963us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 6.390s 216.960us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.110s 209.912us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.460s 372.354us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.460s 372.354us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.460s 129.959us 1 1 100.00
rom_ctrl_csr_rw 3.580s 554.115us 1 1 100.00
rom_ctrl_csr_aliasing 4.820s 535.762us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.520s 661.023us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.460s 129.959us 1 1 100.00
rom_ctrl_csr_rw 3.580s 554.115us 1 1 100.00
rom_ctrl_csr_aliasing 4.820s 535.762us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.520s 661.023us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.880s 3011.642us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.690s 408.527us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 209.580s 1239.310us 1 1 100.00
rom_ctrl_tl_intg_err 25.410s 239.607us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 209.580s 1239.310us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 209.580s 1239.310us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.880s 3011.642us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.880s 3011.642us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.880s 3011.642us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.880s 3011.642us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.880s 3011.642us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 209.580s 1239.310us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 209.580s 1239.310us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.580s 464.386us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.580s 464.386us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.580s 464.386us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 25.410s 239.607us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.880s 3011.642us 1 1 100.00
rom_ctrl_kmac_err_chk 6.390s 216.960us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.880s 3011.642us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.880s 3011.642us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 53.880s 3011.642us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.690s 408.527us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 209.580s 1239.310us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 27.050s 952.547us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 7654824727789616750869790539383038775020087377995078334152746588099467845127 79
UVM_INFO @ 83536582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---