Simulation Results: rom_ctrl/64kb

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.08 %
  • code
  • 97.07 %
  • assert
  • 96.81 %
  • func
  • 97.37 %
  • line
  • 99.46 %
  • branch
  • 99.64 %
  • cond
  • 97.47 %
  • toggle
  • 95.47 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 9.100s 1112.778us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 14.260s 4000.203us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 7.050s 299.537us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.520s 922.210us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.900s 384.402us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.820s 218.399us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 7.050s 299.537us 1 1 100.00
rom_ctrl_csr_aliasing 5.900s 384.402us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.920s 532.009us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.970s 642.376us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 7.110s 501.616us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 26.080s 756.070us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 13.630s 394.999us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 5.530s 906.939us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 10.040s 1939.989us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 10.040s 1939.989us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 14.260s 4000.203us 1 1 100.00
rom_ctrl_csr_rw 7.050s 299.537us 1 1 100.00
rom_ctrl_csr_aliasing 5.900s 384.402us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.590s 540.652us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 14.260s 4000.203us 1 1 100.00
rom_ctrl_csr_rw 7.050s 299.537us 1 1 100.00
rom_ctrl_csr_aliasing 5.900s 384.402us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.590s 540.652us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 117.340s 11966.587us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 40.310s 13921.737us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 456.170s 2472.951us 1 1 100.00
rom_ctrl_tl_intg_err 53.920s 489.264us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 456.170s 2472.951us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 456.170s 2472.951us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 117.340s 11966.587us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 117.340s 11966.587us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 117.340s 11966.587us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 117.340s 11966.587us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 117.340s 11966.587us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 456.170s 2472.951us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 456.170s 2472.951us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 9.100s 1112.778us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 9.100s 1112.778us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 9.100s 1112.778us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 53.920s 489.264us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 117.340s 11966.587us 1 1 100.00
rom_ctrl_kmac_err_chk 13.630s 394.999us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 117.340s 11966.587us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 117.340s 11966.587us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 117.340s 11966.587us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 40.310s 13921.737us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 456.170s 2472.951us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 49.370s 7571.144us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 94759261148174127165284029731843732108175534493229956019530782553733241608405 79
UVM_INFO @ 501615829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---