Simulation Results: rstmgr

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.46 %
  • code
  • 99.24 %
  • assert
  • 98.13 %
  • func
  • 95.02 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.47 %
  • toggle
  • 99.16 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.280s 294.491us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.920s 155.822us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.950s 75.448us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.380s 1435.116us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.920s 403.700us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.220s 228.579us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.950s 75.448us 1 1 100.00
rstmgr_csr_aliasing 1.920s 403.700us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.040s 178.398us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.600s 200.148us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.110s 102.119us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.780s 1789.082us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.780s 1789.082us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.780s 1789.082us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.780s 1789.082us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 1.090s 246.412us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.810s 66.109us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.380s 128.119us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.380s 128.119us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.920s 155.822us 1 1 100.00
rstmgr_csr_rw 0.950s 75.448us 1 1 100.00
rstmgr_csr_aliasing 1.920s 403.700us 1 1 100.00
rstmgr_same_csr_outstanding 1.460s 131.691us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.920s 155.822us 1 1 100.00
rstmgr_csr_rw 0.950s 75.448us 1 1 100.00
rstmgr_csr_aliasing 1.920s 403.700us 1 1 100.00
rstmgr_same_csr_outstanding 1.460s 131.691us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 19.340s 16925.332us 1 1 100.00
rstmgr_tl_intg_err 1.790s 502.276us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 19.340s 16925.332us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 19.340s 16925.332us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.790s 502.276us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.020s 198.575us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 7.010s 2797.760us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.180s 303.418us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 19.340s 16925.332us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.950s 75.448us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.950s 75.448us 1 1 100.00