Simulation Results: rv_timer

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.32 %
  • code
  • 100.00 %
  • assert
  • 98.73 %
  • func
  • 93.24 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.820s 368.621us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.670s 170.186us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.630s 14.094us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.350s 155.779us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.730s 25.491us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.030s 100.368us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.630s 14.094us 1 1 100.00
rv_timer_csr_aliasing 0.730s 25.491us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.620s 127.485us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.780s 2547.731us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 319.700s 372069.667us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 319.700s 372069.667us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.690s 2380.235us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.560s 38.231us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.620s 38.648us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.190s 77.747us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.190s 77.747us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.670s 170.186us 1 1 100.00
rv_timer_csr_rw 0.630s 14.094us 1 1 100.00
rv_timer_csr_aliasing 0.730s 25.491us 1 1 100.00
rv_timer_same_csr_outstanding 0.690s 93.127us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.670s 170.186us 1 1 100.00
rv_timer_csr_rw 0.630s 14.094us 1 1 100.00
rv_timer_csr_aliasing 0.730s 25.491us 1 1 100.00
rv_timer_same_csr_outstanding 0.690s 93.127us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.740s 436.098us 1 1 100.00
rv_timer_tl_intg_err 1.160s 260.567us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.160s 260.567us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.730s 1035.876us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.630s 46.461us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 8.050s 2649.496us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 82685246637920917032419467509702046094815172478982699550053737208867979269678 75
UVM_INFO @ 1035875761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 106335659772002015793429438117201605800253731694663999415568808720227527627271 76
UVM_INFO @ 127485068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 2557758254317730000601470829696263986924128425377882633013605152584363611634 75
UVM_INFO @ 46461122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---