| V1 |
|
100.00% |
| V2 |
|
92.59% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| spi_device_flash_and_tpm | 27.480s | 2339.205us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| spi_device_csr_hw_reset | 0.870s | 53.893us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| spi_device_csr_rw | 2.060s | 386.117us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| spi_device_csr_bit_bash | 18.120s | 4583.124us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| spi_device_csr_aliasing | 7.470s | 1086.096us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| spi_device_csr_mem_rw_with_rand_reset | 1.330s | 487.115us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| spi_device_csr_rw | 2.060s | 386.117us | 1 | 1 | 100.00 | |
| spi_device_csr_aliasing | 7.470s | 1086.096us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| spi_device_mem_walk | 0.730s | 37.324us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| spi_device_mem_partial_access | 1.640s | 120.571us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| csb_read | 1 | 1 | 100.00 | |||
| spi_device_csb_read | 0.710s | 64.974us | 1 | 1 | 100.00 | |
| mem_parity | 0 | 1 | 0.00 | |||
| spi_device_mem_parity | 0.670s | 2.423us | 0 | 1 | 0.00 | |
| mem_cfg | 0 | 1 | 0.00 | |||
| spi_device_ram_cfg | 0.680s | 5.188us | 0 | 1 | 0.00 | |
| tpm_read | 1 | 1 | 100.00 | |||
| spi_device_tpm_rw | 1.600s | 194.091us | 1 | 1 | 100.00 | |
| tpm_write | 1 | 1 | 100.00 | |||
| spi_device_tpm_rw | 1.600s | 194.091us | 1 | 1 | 100.00 | |
| tpm_hw_reg | 2 | 2 | 100.00 | |||
| spi_device_tpm_read_hw_reg | 8.400s | 21047.986us | 1 | 1 | 100.00 | |
| spi_device_tpm_sts_read | 0.950s | 159.648us | 1 | 1 | 100.00 | |
| tpm_fully_random_case | 1 | 1 | 100.00 | |||
| spi_device_tpm_all | 21.250s | 2897.366us | 1 | 1 | 100.00 | |
| pass_cmd_filtering | 2 | 2 | 100.00 | |||
| spi_device_pass_cmd_filtering | 1.850s | 150.187us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 135.550s | 26816.468us | 1 | 1 | 100.00 | |
| pass_addr_translation | 2 | 2 | 100.00 | |||
| spi_device_pass_addr_payload_swap | 4.730s | 7504.236us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 135.550s | 26816.468us | 1 | 1 | 100.00 | |
| pass_payload_translation | 2 | 2 | 100.00 | |||
| spi_device_pass_addr_payload_swap | 4.730s | 7504.236us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 135.550s | 26816.468us | 1 | 1 | 100.00 | |
| cmd_info_slots | 1 | 1 | 100.00 | |||
| spi_device_flash_all | 135.550s | 26816.468us | 1 | 1 | 100.00 | |
| cmd_read_status | 2 | 2 | 100.00 | |||
| spi_device_intercept | 2.230s | 66.210us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 135.550s | 26816.468us | 1 | 1 | 100.00 | |
| cmd_read_jedec | 2 | 2 | 100.00 | |||
| spi_device_intercept | 2.230s | 66.210us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 135.550s | 26816.468us | 1 | 1 | 100.00 | |
| cmd_read_sfdp | 2 | 2 | 100.00 | |||
| spi_device_intercept | 2.230s | 66.210us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 135.550s | 26816.468us | 1 | 1 | 100.00 | |
| cmd_fast_read | 2 | 2 | 100.00 | |||
| spi_device_intercept | 2.230s | 66.210us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 135.550s | 26816.468us | 1 | 1 | 100.00 | |
| cmd_read_pipeline | 2 | 2 | 100.00 | |||
| spi_device_intercept | 2.230s | 66.210us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 135.550s | 26816.468us | 1 | 1 | 100.00 | |
| flash_cmd_upload | 1 | 1 | 100.00 | |||
| spi_device_upload | 3.580s | 443.281us | 1 | 1 | 100.00 | |
| mailbox_command | 1 | 1 | 100.00 | |||
| spi_device_mailbox | 4.220s | 2408.858us | 1 | 1 | 100.00 | |
| mailbox_cross_outside_command | 1 | 1 | 100.00 | |||
| spi_device_mailbox | 4.220s | 2408.858us | 1 | 1 | 100.00 | |
| mailbox_cross_inside_command | 1 | 1 | 100.00 | |||
| spi_device_mailbox | 4.220s | 2408.858us | 1 | 1 | 100.00 | |
| cmd_read_buffer | 2 | 2 | 100.00 | |||
| spi_device_flash_mode | 4.840s | 207.354us | 1 | 1 | 100.00 | |
| spi_device_read_buffer_direct | 7.590s | 1425.946us | 1 | 1 | 100.00 | |
| cmd_dummy_cycle | 2 | 2 | 100.00 | |||
| spi_device_mailbox | 4.220s | 2408.858us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 135.550s | 26816.468us | 1 | 1 | 100.00 | |
| quad_spi | 1 | 1 | 100.00 | |||
| spi_device_flash_all | 135.550s | 26816.468us | 1 | 1 | 100.00 | |
| dual_spi | 1 | 1 | 100.00 | |||
| spi_device_flash_all | 135.550s | 26816.468us | 1 | 1 | 100.00 | |
| 4b_3b_feature | 1 | 1 | 100.00 | |||
| spi_device_cfg_cmd | 3.730s | 1465.798us | 1 | 1 | 100.00 | |
| write_enable_disable | 1 | 1 | 100.00 | |||
| spi_device_cfg_cmd | 3.730s | 1465.798us | 1 | 1 | 100.00 | |
| flash_mode_ignore_cmds | 1 | 1 | 100.00 | |||
| spi_device_flash_mode_ignore_cmds | 42.570s | 5756.868us | 1 | 1 | 100.00 | |
| TPM_with_flash_or_passthrough_mode | 1 | 1 | 100.00 | |||
| spi_device_flash_and_tpm | 27.480s | 2339.205us | 1 | 1 | 100.00 | |
| tpm_and_flash_trans_with_min_inactive_time | 1 | 1 | 100.00 | |||
| spi_device_flash_and_tpm_min_idle | 30.710s | 18163.185us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| spi_device_stress_all | 323.270s | 570828.328us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| spi_device_alert_test | 0.650s | 32.522us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| spi_device_intr_test | 0.730s | 16.180us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| spi_device_tl_errors | 3.080s | 85.749us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| spi_device_tl_errors | 3.080s | 85.749us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| spi_device_csr_hw_reset | 0.870s | 53.893us | 1 | 1 | 100.00 | |
| spi_device_csr_rw | 2.060s | 386.117us | 1 | 1 | 100.00 | |
| spi_device_csr_aliasing | 7.470s | 1086.096us | 1 | 1 | 100.00 | |
| spi_device_same_csr_outstanding | 1.610s | 259.216us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| spi_device_csr_hw_reset | 0.870s | 53.893us | 1 | 1 | 100.00 | |
| spi_device_csr_rw | 2.060s | 386.117us | 1 | 1 | 100.00 | |
| spi_device_csr_aliasing | 7.470s | 1086.096us | 1 | 1 | 100.00 | |
| spi_device_same_csr_outstanding | 1.610s | 259.216us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| spi_device_sec_cm | 0.910s | 66.860us | 1 | 1 | 100.00 | |
| spi_device_tl_intg_err | 4.530s | 429.765us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| spi_device_tl_intg_err | 4.530s | 429.765us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) | 1 test run | |||
| spi_device_mem_parity | 13399923690652509904040496098635370741762188086594945574761981098227427266018 | 76 |
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1848871 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1848871 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1004])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
|
|
| UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) | 1 test run | |||
| spi_device_ram_cfg | 89347694144008516142846689033839844369351963807245187233168334957784227023504 | 76 |
UVM_ERROR @ 2829274 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcd1a66 [110011010001101001100110] vs 0x0 [0])
UVM_ERROR @ 2888274 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x63512d [11000110101000100101101] vs 0x0 [0])
UVM_ERROR @ 2982274 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x46179a [10001100001011110011010] vs 0x0 [0])
UVM_ERROR @ 3068274 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x53b565 [10100111011010101100101] vs 0x0 [0])
|
|