Simulation Results: sram_ctrl/main

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.92 %
  • code
  • 94.67 %
  • assert
  • 97.69 %
  • func
  • 95.40 %
  • block
  • 94.69 %
  • line
  • 95.28 %
  • branch
  • 91.59 %
  • toggle
  • 91.79 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 1463.978us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 38.400us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 7.000s 40.550us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 428.078us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 13.457us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 753.538us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 7.000s 40.550us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 13.457us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 95.000s 10953.068us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 48.000s 11069.820us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 13.000s 3404.481us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 154.000s 5694.176us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 121.000s 4358.791us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 43.000s 22409.271us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 52.000s 83460.240us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 34.000s 44332.882us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 876.177us 1 1 100.00
sram_ctrl_partial_access_b2b 194.000s 16180.423us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 4.000s 2663.162us 0 1 0.00
sram_ctrl_throughput_w_partial_write 5.000s 2876.533us 0 1 0.00
sram_ctrl_throughput_w_readback 3.000s 693.937us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 9.000s 12249.288us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 1391.502us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 202.000s 55642.636us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 38.477us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 561.744us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 561.744us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 38.400us 1 1 100.00
sram_ctrl_csr_rw 7.000s 40.550us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 13.457us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 18.874us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 38.400us 1 1 100.00
sram_ctrl_csr_rw 7.000s 40.550us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 13.457us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 18.874us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 12.000s 3861.954us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 806.091us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 148.475us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 806.091us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 148.475us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 12249.288us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 12249.288us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 7.000s 40.550us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 34.000s 44332.882us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 34.000s 44332.882us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 34.000s 44332.882us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 52.000s 83460.240us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 2837.890us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 12.000s 3861.954us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.000s 3182.874us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 1463.978us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 1463.978us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 34.000s 44332.882us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 806.091us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 52.000s 83460.240us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 806.091us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 806.091us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 1463.978us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 806.091us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 26.000s 986.756us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 12568135141258087812029814150135741407844239949265474963510086366971667225713 86
UVM_INFO @ 2663162000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 73373398141058439353113871575217345841188803632220789358605914352319461106908 86
UVM_INFO @ 2876532543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 113088163950190597049969947874134274716634499338326143410006404824876952727404 86
UVM_INFO @ 693936684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---