Simulation Results: sram_ctrl/ret

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.00 %
  • code
  • 81.00 %
  • assert
  • 97.39 %
  • func
  • 94.60 %
  • block
  • 92.00 %
  • line
  • 92.97 %
  • branch
  • 86.07 %
  • toggle
  • 78.31 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 226.701us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 36.481us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.231us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 214.046us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 59.397us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 34.217us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 15.231us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 59.397us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 8.000s 828.067us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.000s 158.305us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 8.000s 1292.445us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 101.000s 2031.583us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 7.000s 535.800us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 6.000s 708.153us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.000s 938.781us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 9.000s 1681.740us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 77.070us 1 1 100.00
sram_ctrl_partial_access_b2b 155.000s 12691.656us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 1.000s 22.652us 0 1 0.00
sram_ctrl_throughput_w_partial_write 2.000s 51.524us 0 1 0.00
sram_ctrl_throughput_w_readback 2.000s 120.152us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 2.000s 81.654us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 32.549us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 27.000s 5628.894us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 12.623us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 147.505us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 147.505us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 36.481us 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.231us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 59.397us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 112.195us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 36.481us 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.231us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 59.397us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 112.195us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 268.070us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 7001.395us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 534.982us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 7001.395us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 534.982us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 2.000s 81.654us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 2.000s 81.654us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.231us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 9.000s 1681.740us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 1681.740us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 1681.740us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.000s 938.781us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 125.583us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 268.070us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 38.779us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 226.701us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 226.701us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 9.000s 1681.740us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 7001.395us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.000s 938.781us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 7001.395us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 7001.395us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 226.701us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 7001.395us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 51.000s 3156.378us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 79137919756156151038262888191708822771371511501062620894050238097621106428353 86
UVM_INFO @ 22651616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 34138049912174177100399417554134145133562397237837859254389843585499708498849 86
UVM_INFO @ 51524085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 4690822339733618242365461119719468450049103125437263274045419677005957223717 86
UVM_INFO @ 120151710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---