Simulation Results: sysrst_ctrl

 
24/06/2026 15:30:34 DVSim: v1.49.11 sha: 18ef53a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.60 %
  • code
  • 93.14 %
  • assert
  • 93.20 %
  • func
  • 64.47 %
  • line
  • 97.17 %
  • branch
  • 97.33 %
  • cond
  • 94.92 %
  • toggle
  • 100.00 %
  • FSM
  • 76.28 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.390s 2166.500us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 2.910s 2484.395us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 0.850s 2513.802us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.330s 2280.037us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 2.170s 4053.199us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 3.330s 2072.332us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 72.320s 75162.632us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 4.020s 3195.381us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.990s 2188.480us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 3.330s 2072.332us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.020s 3195.381us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 42.840s 101643.182us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 90.470s 109925.505us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 2.150s 3483.149us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 8.440s 4930.668us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.860s 2532.075us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 3.180s 2104.441us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 4.620s 4285.363us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 2.620s 2623.477us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 2.090s 9667.065us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 31.000s 37341.504us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 3.240s 14212.121us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 2.000s 2026.771us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.400s 2021.060us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 5.090s 2041.407us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 5.090s 2041.407us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.170s 4053.199us 1 1 100.00
sysrst_ctrl_csr_rw 3.330s 2072.332us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.020s 3195.381us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 7.840s 9832.761us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.170s 4053.199us 1 1 100.00
sysrst_ctrl_csr_rw 3.330s 2072.332us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.020s 3195.381us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 7.840s 9832.761us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 17.450s 42146.976us 1 1 100.00
sysrst_ctrl_tl_intg_err 40.190s 22252.177us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 40.190s 22252.177us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 9.170s 22566.007us 1 1 100.00